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HI5634 Datasheet(PDF) 6 Page - Intersil Corporation |
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HI5634 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 16 page  6 Specific Layout Guidelines 1. Digital Supply (VDDD) - Bypass pin 1 (VDDD) to pin 2 (VSSD) with 4.7 µF and 0.1µF capacitors, located as close as possible to the pins. Traces must be maximally wide and include multiple surface-etched vias to the ap- propriate plane. 2. External Loop Filter - The use of an external loop filter is strongly recommended in all designs. Locate loop fil- ter components as close to pins 8 and 9 (EXTFIL and EX- TFILRET) as possible. Typical loop filter values are 6.8k Ω for the series resistor, 3300pF RF-type capacitor for the se- ries capacitor, and 150pF for the shunt capacitor. 3. Analog PLL Supply (VDDA) - Decouple pin 10 (VDDA) with a series ferrite bead. Bypass the supply end of the bead with 4.7 µF and 0.1µF capacitors. Bypass pin 10 to pin 11 (VSSA) with a 0.1 µF capacitor. Locate these com- ponents as close as possible to the pins. Traces must be maximally wide and have multiple surface-etched vias to the power or ground planes. 4. PECL Current Set Resistor - Locate PECL current set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to ground with a 0.1 µF capacitor. 5. PECL Outputs - Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 Ω characteristic impedance, presuming 0.067 in. between layers. Locate the optional series “snubbing” resistors as close as possible to the pins. If the termination resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground planes (these termination resistors are omitted if the load device implements them internally). 6. Output Driver Supply (VDDQ) - Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with 4.7 µF and 0.1µF capacitors, locat- ed as close as possible to the pins. Traces must be max- imally wide and include multiple surface-etched vias to the appropriate plane. 7. SSTL_3 Outputs - SSTL_3 outputs can be used like con- ventional CMOS rail-to-rail logic or as a terminated trans- mission line system at higher-output frequencies. With terminated outputs, the considerations of item 5, “PECL Outputs” apply. See JEDEC documents JESD8-A and JESD8-8. Power Supply Considerations The HI5634 incorporates special internal power-on-reset circuitry that requires no external reset signal connection. The supply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the HI5634, the supply voltage at the part must be reduced below the threshold voltage (VTH) of the power-on- reset circuit. The supply voltage must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset state is latched. The amount of time (tD) to hold the voltage in a reset state varies with the design. However, a typical value of 10ms should be sufficient. SSTL_3 Outputs Unterminated Outputs In the HI5634, unterminated SSTL output pins display exponential transitions similar to those of rectangular pulses presented to RC loads. The 10-90% rise time is typically 1.6ns, and the corresponding fall time is typically 700ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor determining high frequency performance of these single-ended outputs. Typically, no termination is required for the LOCK/REF, FUNC, and CLK/2 outputs nor for CLK outputs up to approximately 135MHz. Terminated Outputs SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance. Use of transmission line techniques enables use of longer traces between source and driver without increasing ringing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet LVTTL VIH and VIL requirements, the intrinsic rise and fall times of HI5634 SSTL outputs are only slightly improved by termination in a low impedance. The HI5634 SSTL output source impedance is typically less than 60 Ω. Termination impedance of 100Ω reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs. VMIN VTH = 1.8V tD VDD HI5634 SINGLE LVTTL LOAD SSTL_3 OUTPUT VDD 330 Ω 150 Ω HI5634 |
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