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HIP6011 Datasheet(PDF) 7 Page - Intersil Corporation

Part # HIP6011
Description  Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HIP6011 Datasheet(HTML) 7 Page - Intersil Corporation

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7
The compensation network consists of the error amplifier
(internal to the HIP6011) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to pro-
vide a closed loop transfer function with the highest 0dB
crossing frequency (f0dB) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f0dB and 180 degrees. The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use
these guidelines for locating the poles and zeros of the com-
pensation network:
1) Pick Gain (R2/R1) for Desired Converter Bandwidth
2) Place 1STZero Below Filter’s Double Pole (~75% FLC)
3) Place 2ND Zero at Filter’s Double Pole
4) Place 1ST Pole at the ESR Zero
5) Place 2ND Pole at Half the Switching Frequency
6) Check Gain against Error Amplifier’s Open-Loop Gain
7) Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak do to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying
the
modulator
transfer
function
to
the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the ESR
(effective series resistance) and voltage rating requirements
rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible.
Be careful not to add inductance in the circuit board wiring
that could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel rec-
ommends that the high frequency decoupling for the Pen-
tium-Pro be composed of at least forty (40) 1.0
µF ceramic
capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the use-
fulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s imped-
ance with frequency to select a suitable component. In most
cases, multiple electrolytic capacitors of small case size per-
form better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
F
Z1 =
1
2
π R2 C1
---------------------------------
F
P1 =
1
2
π R2
C1
C2
C1 + C2
----------------------


------------------------------------------------------
F
Z2 =
1
2
π
R1 + R3
()
C3
-----------------------------------------------------
F
P2 =
1
2
π R3
C3
---------------------------------
100
80
60
40
20
0
-20
-40
-60
FP1
FZ2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
FZ1
FP2
FLC
FESR
CLOSED LOOP
COMPENSATION
GAIN
FREQUENCY (HZ)
GAIN
20LOG(VIN/DVOSC)
20LOG(R2/R1)
MODULATOR GAIN
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
∆I=
V
IN -VOUT
Fs
L
O
×
--------------------------------
V
OUT
V
IN
----------------
∆V
OUT = ∆I x ESR
HIP6011


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