2-259

immediately sets the fault latch. A sequence of three over-

current fault signals also sets the fault latch. A comparator

under-voltage event on either linear output (FB3 or FB4) is

ignored until after the soft-start interval (approximately T3 in

up over increased time intervals, without generating a fault.

then on resets the counter and the fault latch.

Over-Voltage Protection

During operation, a short on the upper MOSFET (Q1)

over-voltage threshold of 115% of DACOUT, the over-voltage

comparator trips to set the fault latch and turns Q2 on as

raises the FAULT/RT pin close to VCC potential.

A separate over-voltage circuit provides protection during

the initial application of power. For voltages on the VCC pin

monitored for voltages exceeding 1.26V. Should VSEN1

exceed this level, the lower MOSFET (Q2) is driven on, as

Over-Current Protection

All outputs are protected against excessive over-currents.

Both PWM controllers use the upper MOSFET’s

against shorted outputs. The linear regulator monitors the

current of the integrated power device and signals an over-

current condition for currents in excess of 230mA.

Additionally, both the linear regulator and the linear

controller monitor FB3 and FB4 for under-voltage to protect

against excessive currents.

Figures 8 and 9 illustrate the over-current protection with an

overload on OUT2. The overload is applied at T0 and the

T1, the OVER-CURRENT2 comparator trips when the voltage

with the error amplifiers clamped by soft-start. With OUT2 still

overloaded, the inductor current increases to trip the over-

current comparator. Again, this inhibits all outputs, but the

soft-start voltage continues increasing to 4V before

discharging. The counter increments to 2. The soft-start cycle

repeats at T3 and trips the over-current comparator. The SS

pin voltage increases to 4V at T4 and the counter increments to

3. This sets the fault latch to disable the converter. The fault is

reported on the FAULT/RT pin.

The PWM1 controller and the linear regulator operate in the

same way as PWM2 to over-current faults. Additionally, the

linear regulator and linear controller monitor the feedback

pins for an under-voltage. Should excessive currents cause

FB3 or FB4 to fall below the linear under-voltage threshold,

interval allows the linear outputs to build above the under-

voltage threshold during normal start-up. Cycling the bias

FAULT

LATCH

S

R

Q

POR

COUNTER

OC1

OV

OC2

LUV

+

-

+

-

0.15V

4V

SS

VCC

FAULT

R

FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC

UP

OVER

CURRENT

LATCH

INHIBIT

S

R

Q

S

0A

0V

2V

4V

FIGURE 8. OVER-CURRENT OPERATION

TIME

T1

T2

T3

T0

T4

0V

10V

FAULT

REPORTED

COUNT

= 1

COUNT

= 2

COUNT

= 3

OVERLOAD

APPLIED

HIP6019