2-305

OUT2 Voltage Selection

The AGP regulator output voltage is internally set to one of

two discrete levels, based on the status of the SELECT pin.

SELECT pin is internally pulled ‘high’, such that left open,

the AGP output voltage is by default set to 3.3V. The other

discrete setting available is 1.5V, which can be obtained by

grounding the SELECT pin using a jumper or another

suitable method capable of sinking a few tens of

microamperes. The status of the SELECT pin cannot be

changed during operation of the IC without immediately

causing a fault condition.

OUT3 and OUT4 Voltage Adjustability

The GTL bus voltage (1.5V, OUT3) and the chip set and/or

cache memory voltage (1.8V, OUT4) are internally set for

simple, low-cost implementation in typical Intel motherboard

architectures. However, if different voltage settings are

desired for these two outputs, the FIX pin provides the

necessary adaptability. Left open (NC), this pin sets the fixed

output voltages described above. Grounding this pin allows

both output voltages to be set by means of external resistor

dividers as shown in Figure 7.

Application Guidelines

Soft-Start Interval

Initially, the soft-start function clamps the error amplifier’s

output of the PWM converter. This generates PHASE pulses

of increasing width that charge the output capacitor(s). After

the output voltage increases to approximately 70% of the set

value, the reference input of the error amplifier is clamped to

a voltage proportional to the SS pin voltage. The resulting

output voltages start-up as shown in Figure 3.

The soft-start function controls the output voltage rate of rise

to limit the current surge at start-up. The soft-start interval and

the surge current are programmed by the soft-start capacitor,

peak surge current. The peak surge current occurs during the

initial output voltage rise to 70% of the set value.

Shutdown

The HIP6021 features a dedicated shutdown pin (SD). A

TTL-compatible, logic high signal applied to this pin shuts

down (disables) all four outputs and discharges the soft-start

capacitor. Following a shutdown, a logic low signal

re-enables the outputs through initiation of a new soft-start

cycle. Left open this pin will asses a logic low state, due to its

internal pull-down resistor, thus enabling normal operation of

all outputs.

The PWM output does not switch until the soft-start voltage

on each linear’s error amplifier are clamped to the soft-start

voltage. Holding the SS pin low (with an open drain or

collector signal) turns off all four regulators.

The ‘11111’ VID code also shuts down the IC.

11110

2.1

11101

2.2

11100

2.3

11011

2.4

11010

2.5

11001

2.6

11000

2.7

10111

2.8

10110

2.9

10101

3.0

10100

3.1

10011

3.2

10010

3.3

10001

3.4

10000

3.5

NOTE: 0 = connected to GND, 1 = open or connected to 5V through

pull-up resistors

TABLE 1. OUT1 VOLTAGE PROGRAM (Continued)

PIN NAME

NOMINAL

DACOUT

VOLTAGE

VID4

VID3

VID2

VID1

VID0

DRIVE3

VSEN3

VSEN4

Q4

HIP6021

Q5

DRIVE4

VAUX

FIX

V

OUT

V

BG

1

R

S

R

P

--------

+







×

=

FIGURE 7. ADJUSTING THE OUTPUT VOLTAGE OF

OUTPUTS 3 AND 4

HIP6021