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HIP7010B Datasheet(PDF) 2 Page - Intersil Corporation |
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HIP7010B Datasheet(HTML) 2 Page - Intersil Corporation |
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2 / 20 page  2 Block Diagram 10 9 SOUT SIN 7 6 5 12 TEST VSS 11 CLK 13 14 1 8 STAT RDY SCK 2 3 VPWOUT GENERATOR TIMING STATE MACHINE AND CONTROL LOGIC DECODED VPW IN OUTPUT DATA J1850 VPW SYMBOL ENCODER/DECODER LSB MSB STATUS/CONTROL BYTE VDD 4 A B C MUX CRC GENERATOR/CHECKER A B MUX DATA SHIFT REGISTER IDLE RESET SACTIVE VPWIN Pin Description PIN NUMBER PIN NAME IN/OUT PIN DESCRIPTION 1 IDLE OUT CMOS Output 2 VPWIN IN CMOS Schmitt (No VDD Diode) 3 VPWOUT OUT CMOS Output 4VDD - Power Supply 5 RESET IN CMOS Schmitt (No VDD Diode) 6 TEST IN CMOS Input with Pull-Down 7 SACTIVE OUT CMOS Output 8 SCK OUT Three-State with Pull-Down 9 SOUT OUT Three-State with Pull-Down 10 SIN IN CMOS Input with Pull-Down 11 VSS - Ground 12 CLK IN CMOS Schmitt (No VDD Diode) 13 STAT IN CMOS Input with Pull-Down 14 RDY IN CMOS Input with Pull-Down HIP7010 |
Similar Part No. - HIP7010B |
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Similar Description - HIP7010B |
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