ADG936R_15 datasheet(6/17 Pages) AD

Part #	ADG936R

Description	CMOS, 1.65 V to 2.75 V, Dual SPDT

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Data Sheet

ADG936/ADG936-R

Rev. B | Page 5 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

20

19

18

17

16

15

14

13

VDD

GND

RF1A

GND

RF1B

GND

INA

GND

RF2A

GND

RF2B

GND

ADG936

ADG936-R

TOP VIEW

(Not to Scale)

RFCA

9

10

12

11

GND

RFCB

INB

GND

NOTES

1. EXPOSED PAD TIED TO SUBSTATE, GND.

14

13

12

1

3

4

RF2A

15 GND

GND

11 RF2B

GND

2

RF1A

GND

5

RF1B

ADG936

ADG936-R

TOP VIEW

(Not to Scale)

Figure 5. 20-Lead TSSOP (RU-20)

Figure 6. 20-Lead 4 mm × 4 mm LFCSP (CP-20-1)

Table 4. Pin Function Descriptions

Pin No.

20-Lead

TSSOP

20-Lead

LFCSP

Mnemonic

Description

1

18

RFCA

Common RF Port for Switch A.

2

19

VDD

Power Supply Input. These parts can operate from 1.65 V to 2.75 V. VDD should be decoupled

to GND.

3, 5, 6, 8, 9,

11, 13, 15,

16, 18, 20

1, 3, 4, 6, 7,

9, 12, 13,

15, 17, 20

GND

Ground Reference Point for All Circuitry on the Part.

4

2

RF1A

RF1A Port.

7

5

RF1B

RF1B Port.

10

8

RFCB

Common RF Port for Switch B.

12

10

INB

Logic Control Input.

14

11

RF2B

RF2B Port.

17

14

RF2A

RF2A Port.

19

16

INA

Logic Control Input.

EP

Exposed Pad. The exposed pad must be tied to substrate, GND.

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