5-189

Transmitter Operation

The Transmitter section consists of an 8-word deep by 31-

Bit long FIFO Memory, Parity Generator, Transmitter Word

Gap Timing Circuit and Driver Circuit.

• The FlFO Memory is organized in such a way that data

loaded in the input register is automatically transferred to

the output register for Serial Data Transmission. This

eliminates a large amount of data managing time since the

data need not be clocked from the input register to the

output register. The FIFO input register is made up of two

sets of 16 D-type flip-flops, which are clocked by the two

parallel load signals (PL1 and PL2). PL1 must always

precede PL2. Multiple PL1’s may occur and data will be

written over. As soon as PL2 is received, data is

transferred to the FIFO. The data from the Data Bus is

clocked into the D-type flip-flop on the positive going edge

of the PL signals. If the FIFO memory is initially empty, or

the stack is not full, the data will be automatically

transferred down the Memory Stack and into the output

register or to the last empty FIFO storage register. If the

Transmitter Enable signal (ENTX) is not active, a Logic “0”,

the data remains at the output register. The FIFO Memory

has storage locations to hold eight 31-bit words. If the

memory is full and the new data is again strobed with PL,

the old data at the input register is written over by the new

data. Data will remain in the Memory until ENTX goes to a

Logic “1”. This activates the FIFO Clock and data is shifted

out serially to the Transmitter Driver. Data may be loaded

into the FIFO only while ENTX is inactive (low). It is not

possible to write data into the FIFO while transmitting.

WARNING: If PL1 or PL2 is applied while ENTX is high,

i.e., while transmitting, the FlFO may be disrupted such

that it would require a MR (Master Reset) signal to

recover.

• The Output Register of the FIFO is designed such that it

can shift out a word of 24 Bits long or 31 Bits long. This

word length is again controlled by the WLSEL bit. The TX

word Gap Timer Circuit also automatically inserts a gap

equivalent to 4-Bit Times between each word. This gives a

minimum requirement of 29-Bit time or 36-Bit time for each

word transmission. Assuming the signal, ENTX, remains

at a Logic “1”, a transfer to stack signal is generated to

transfer the data down the Memory Stack one position.

This action is continued until the last word is shifted out of

the FIFO memory. At this time a Transmitter Ready (TX/R)

flag is generated to signal the user that the Transmitter is

ready to receive eight more data words. During transmis-

sion, if ENTX is taken low then high again, transmission

will cease leaving a portion of the word untransmitted, and

the data integrity of the FIFO will be destroyed.

• A Bit Counter is used to detect the last Bit shifted out of

the FIFO memory and appends the Parity Bit generated

by the Parity Generator. The Parity Generator has a

control signal, Parity Check (PARCK), which establishes

whether odd or even parity is used in the output data word.

PARCK set to a logic “0” will result in odd parity and when

set to a logic “1” will result in even parity.

Sample Interface Technique

From Figure 1, one can see that the Data Bus is time shared

between the Receiver and Transmitter. Therefore, bus

controlling must be synchronously shared between the

Receiver and the Transmitter.

Figure 2 shows the typical interface timing control of the

ARlNC Chip for Receiving function and for Transmitting

function. Timing sequence for loading the Transmitter FIFO

Memory is shown in Timing Interval A. A transmitter Ready

(TX/R) Flag signals the user that the Transmitter Memory is

empty. The user then Enables the Transmitter Data, a 16-Bit

word, on the Data Bus and strobes the Transmitter with a

Parallel Load (PL1) Signal. The second part of the 32-Bit

word is similarly loaded into the Transmitter with PL2, which

also initiates data transfer to stack. This is continuous until

the Memory is full, which is eight 31-Bit words. The user

must keep track of the number of words loaded into the

Memory to ensure no data is written over by other data.

During the time the user is loading the Transmitter, he does

not have to service the Receiver, even if the Receiver flags

the user with the signal D/R1 that a valid received word is

ready to be fetched. This is shown by the Timing interval B. If

the user decides to obtain the received data before the

Transmitter is completely loaded, he sets the two parallel

load signals (PL1 and PL2) at a Logic “1” state, and strobes

EN1 while the signal SEL is at a Logic “0” state. After the

negative edge of EN1, the first 16-Bit segment of the

received word becomes valid on the Data Bus. At the

positive edge of EN1, the user should toggle the signal SEL

to ready the Receiver for the second 16-Bit word. Strobing

the Receiver with EN1, the second time, enables the second

16-Bit word and resets the Receiver Ready Flag D/R1. The

user should now reset the signal SEL to a Logic “0” state to

ready the Receiver for another Read Cycle. During the time

period that the user is fetching the received words, he can

load the transmitter. This is done by interlacing the PL

signals with the EN signals as shown in the Timing Interval

B. Servicing the Receiver 2 is similar and is illustrated by

Timing interval C. Timing interval D shows the rest of the

Transmitter loading sequence and the beginning of the

transmission by switching the signal TX Enable to a Logic “1”

state. Timing interval E is the time it takes to transmit all data

from the FlFO Memory, either 288 Bit times or 232 Bit times.

Repeater Operation

This mode of operation allows a data word that has been

received to be placed directly in the FIFO for transmission. A

timing diagram is shown in Figure 7. A 32-bit word is used in

this example. The data word is shifted into the shift register

and the D/R flag goes low. A logic “0” is placed on the SEL

line and EN1 is strobed. This is the same as the normal

receiver operation and places half the data word (16 bits) on

the data bus. By strobing PL1 at the same time as EN1,

these 16 bits will be taken off the bus and placed in the

FIFO. SEL is brought back high and EN1 is strobed again for

the second 16 bits of the data word. Again by strobing PL2 at

the same time the second 16 bits will be placed in the FIFO.

The parity bit will have been stripped away leaving the 31-bit

data word in the FIFO ready for transmission as shown in

Figure 6.

HS-3282