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ADG3123 Datasheet(PDF) 10 Page - Analog Devices |
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ADG3123 Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page ADG3123 Data Sheet Rev. B | Page 10 of 12 THEORY OF OPERATION The ADG3123 is an 8-channel, noninverting CMOS to high voltage level translator. Fabricated on an enhanced LC2MOS process, the device is capable of operating at high supply voltages while maintaining ultralow power consumption. The device requires a dual-supply voltage, VDDB and VSS, which sets the low logic levels for all outputs and the high logic levels for the Y7 and Y8 outputs. The VDDA pin acts as an analog input. The voltage applied to the VDDA pin sets the output high logic level for the Y1 to Y6 outputs. The device translates the CMOS logic levels applied to the A1 to A8 inputs into high voltage bipolar levels available on the Y side of the device at Pin Y1 to Pin Y8. To ensure proper operation, VDDB must always be greater than or equal to VDDA and the voltage between the Pin VDDB and Pin VSS should not exceed 35 V. INPUT DRIVING REQUIREMENTS The ADG3123 design ensures low input capacitance and leakage current thereby reducing the loading of the circuit that drives the input pins (Pin A1 to Pin A8) to a minimum. Its input threshold levels are compliant with JEDEC standards for drivers operated from supply voltages between 2.3 V and 5.5 V. It is recommended that the inputs of any unused channel be tied to a stable logic level (low or high). OUTPUT LOAD REQUIREMENTS The low output impedance of the ADG3123 allows each channel to drive both resistive and capacitive loads. The maximum load current is limited by the current carrying capability of any given channel. If more channels are used, the maximum load current per channel is reduced accordingly. Note that the sum of the load currents on all channels should never exceed the absolute maximum ratings specifications. The average load current on each channel, ICHANNEL, can be determined using the formulas shown in the Capacitive Loads and the Resistive Loads sections. Capacitive Loads ICHANNEL (A) = FO × CL × (VDDX + |VSS|) where: FO is the frequency of the signal applied to the channel in Hz. CL is the load capacitance in farads. VSS is the voltage applied to the VSS pin. VDDX is VDDA for Y1 to Y6 outputs, and VDDB for Y7 to Y8 outputs. Resistive Loads L SS DDX CHANNEL R V D V D A I × − + × = ) 1 ( ) ( where: D is the duty cycle of the input signal. D is defined as the ratio between the high state duration of the signal and its period. RL is the load resistor in Ω. VSS is the voltage applied to the VSS pin. VDDX is VDDA for Y1 to Y6 outputs, and VDDB for Y7 to Y8 outputs. POWER SUPPLIES The ADG3123 operates from a dual-supply voltage. As good design practice for all CMOS devices dictates, power up the ADG3123 first (VDDB and VSS) before applying the signals to its inputs (A1 to A8 and VDDA). To ensure correct operation of the ADG3123, the voltage applied to the VDDB pin must always be greater than or equal to VDDA and the voltage between the Pin VDDB and Pin VSS should not exceed 35 V. To ensure optimum performance, use decoupling capacitors on all power supply pins. Furthermore, good engineering and layout practice suggests placing these capacitors as close as possible to the package supply pins. |
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