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HS9-81C55RH Datasheet(PDF) 10 Page - Intersil Corporation |
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HS9-81C55RH Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 14 page 10 HS-81C55RH, HS-81C56RH Functional Description The HS-81C55RH and 81C56RH contains the following: • 2K Bit Static RAM Organized as 256 x 8 • Two 8-Bit I/O Ports (PA and PB) and One 6-Bit I/O Port (PC) • 14-Bit Timer-Counter The IO/M (IO/Memory Select) pin selects either the five reg- ister (Command, Status, PA0 - PA7, PB0 - PB7, PC0 - PC5) or the memory (RAM) portion. The 8-bit address on the Address/Data lines, Chip Enable input CE or CE and IO/M are all latched on-chip at the falling edge of ALE. FIGURE 1. INTERNAL REGISTERS FIGURE 2. ON-BOARD MEMORY READ/WRITE CYCLE Programming of the Command Register The command register consists of eight latches. Four bits (0- 3) define the mode of the ports, two bit (4-5) enable or disable the interrupt from port C when it acts as control port, and the last two bits (6-7) are for the timer. The command register contents can be altered at anytime by using the I/O address XXXXX000 during a WRITE operation with the Chip Enable active and IO/M = 1. The meaning of each bit of the command byte is defined in Figure 3. The contents of the command register may never be read. FIGURE 3. COMMAND REGISTER BIT ASSIGNMENT Reading the Status Register The status register consists of seven latches, one for each bit six (0-5) for the status of the ports and one (6) for the status of the timer. The status of the timer and the I/O section can be polled by reading the Status Register (Address XXXXX000). Status word format is shown in Figure 4. Note that you may never write to the status register since the command register shares the same I/O address and the command register is selected when a write to that address is issued. FIGURE 4. STATUS REGISTER BIT ASSIGNMENT COMMAND STATUS PC PB PA TIMER MSB TIMER LSB 8-BIT INTERNAL DATA BUS 6 8 8 TIMER MODE CE (81C55RH) OR CE (81C56RH) IO/M AD0 - AD7 ALE RD OR WR ADDRESS DATA VALID TM2 TM1 IEB IEA PC2 PC1 PB PA 76543210 DEFINES DEFINES DEFINES ENABLE PORT A INTERRUPT ENABLE PORT B INTERRUPT 00 = NOP - DO NOT AFFECT COUNTER OPERATION 01 = STOP - NOP IF TIMER HAS NOT STARTED; STOP COUNTING IF THE TIMER IS RUNNING 10 = STOP AFTER TC - STOP IMME- DIATELY AFTER PRESENT TC IS REACHED (NOP IF TIMER HAS NOT STARTED) 11 = START - LOAD MODE AND CNT LENGTH AND START IMMEDIATE- LY AFTER LOADING (IF TIMER IS NOT PRESENTLY RUNNING). IF TIMER IS RUNNING, START THE NEW MODE AND CNT LENGTH IMMEDIATELY AFTER PRESENT TC IS REACHED. 0 = INPUT 1 = OUTPUT 00 = ALT1 11 = ALT2 01 = ALT3 10 = ALT4 0 = INPUT 1 = OUTPUT PA0 - PA7 PB0 - PB7 PC0 - PC5 TIMER COMMAND TIMER INTE B B BF INTR B INTE A A BF INTR A AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PORT A INTERRUPT REQUEST PORT A BUFFER FULL/EMPTY (INPUT/OUTPUT) PORT A INTERRUPT ENABLE PORT B INTERRUPT REQUEST PORT B BUFFER FULL/EMPTY (INPUT/OUTPUT) PORT B INTERRUPT ENABLE TIMER INTERRUPT (THIS BIT IS LATCHED HIGH WHEN TERMINAL COUNT IS REACHED, AND IS RESET TO LOW READING OF THE C/S REGISTER & BY HARDWARE RESET). Spec Number 518056 |
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Similar Description - HS9-81C55RH |
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