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HSP43124PC-45 Datasheet(PDF) 4 Page - Intersil Corporation |
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HSP43124PC-45 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 17 page 4 Functional Descriptions The HSP43124 is a high performance digital filter designed to process a serial input data stream. A second serial interface is provided for mix factor inputs, which are multiplied by the input samples as shown in Figure 1. The multiplier result is passed to the Filter Compute Engine for processing. The Filter Compute Engine centers around a single multiply/accumulator (MAC). The MAC performs the sum-of- products required by a particular filter configuration. The processing rate of the MAC is determined by the filter clock, FCLK. Increasing FCLK relative to the input sample rate increases the length of filter that can be realized. The filtered results are passed to the Output Formatter where they are rounded or truncated to a user defined bit width. The Output Formatter then generates the timing and synchronization signals required to serially transmit the data to an external device. Filter Configuration The HSP43124 is configured for operation by loading a set of eight control registers. These registers are written through a bidirectional interface which is also used for reading the control registers. The interface consists of an 8-bit data bus, C0-7, a 3-bit address bus, A0-2, and read/write lines, RD and WR. The address map for the control registers is shown in Table 1. Data is written to the configuration control registers on the falling edge of the WR input. This requires that the address, A0-2, and data, C0-7, be stable and valid on the falling edge of the WR, as shown in Figure 2. NOTE: WR should not be active low when RD is active low. Data is read from the configuration control registers on the falling edge of the RD input. The contents of a particular register are accessed by setting up an address, A0-2, to the falling edge of RD as shown in Figure 2. The data is output on C0-7. The data on C0-7 remains valid until RD returns HIGH, at which point the C0-7 bus is Three-Stated and functions as an input. For proper operation, the address on A0-2 must be held until RD returns “high” as shown in Figure 2. NOTE: RD should not be active low when WR is active low. M U X MUX HOLDING REG MIX FACTOR HOLDING SERIAL MULTIPLIER ROUND/ SATURATE COEFFICIENT RAM R E G VARIABLE LENGTH SHIFT REGISTER (8 TO 24 BITS) + ROUND/ SATURATE WEAVER MODULATOR ROM MUX CONTROL MXIN SYNCIN 25 24 32 48 57 HALFBAND COEFFICIENT ROM REG REGISTER FILE + VARIABLE LENGTH SHIFT REGISTER (8-24-BITS) DIN SYNCIN SYNCMX MXIN A0-2 C0-7 WR RD FSYNC FCLK SCLK MULTIPLY/ INPUT FORMATTER FILTER COMPUTE ENGINE SYNCMX OUTPUT FORMATTER ACCUMULATOR DOUT SYNCOUT CLKOUT FIGURE 1. SERIAL FILTER BLOCK DIAGRAM INPUT # BITS † MSB F/2 † FORMAT † MIX SEL † # BITS † FORMAT † FILT EN † # HBs † † † DECIMATION RATE † FIR SYM † RD EN † FILTER LENGTH † RAM ACCESS † ROUND † FORMAT † GAIN COR † # BITS † FCLK † MSB F/L † CLKOUT †Indicates configuration control word data parameter. CONTROL PARAMETERS WR A0-2 WRITE TIMING C0-7 RD A0-2 READ TIMING C0-7 FIGURE 2. READ/WRITE TIMING HSP43124 |
Similar Part No. - HSP43124PC-45 |
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Similar Description - HSP43124PC-45 |
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