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HSP43891VC-25 Datasheet(PDF) 1 Page - Intersil Corporation |
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HSP43891VC-25 Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 18 page 1 File Number 2785.5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HSP43891 Digital Filter The HSP43891 is a video-speed Digital Filter (DF) designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a 9x9 two’s complement multiplier, three decimation registers and a 26-bit accumulator. The output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8-bits. The HSP43891 has a maximum sample rate of 30MHz. The effective multiply-accumulate (mac) rate is 240MHz. The HSP43891 DF can be configured to process expanded coefficient and word sizes. Multiple DFs can be cascaded for larger filter lengths without degrading the sample rate or a single DF can process larger filter lengths at less than 30MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. The DF provides for 8-bit unsigned or 9-bit two’s complement arithmetic, independently selectable for coefficients and signal data. Each DF filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1/2, 1/ 3 or 1/ 4 the input sample rate. These registers also provide the capability to perform 2-D operations such as matrix multiplication and NxN spatial correlations/convolutions for image processing applications. Features • Eight Filter Cells • 0MHz to 30MHz Sample Rate • 9-Bit Coefficients and Signal Data • 26-Bit Accumulator per Stage • Filter Lengths Over 1000 Taps • Expandable Coefficient Size, Data Size and Filter Length • Decimation by 2, 3 or 4 Applications • 1-D and 2-D FIR Filters • Radar/Sonar • Digital Video • Adaptive Filters • Echo Cancellation • Complex Multiply-Add - Sample Rate Converters Block Diagram Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HSP43891VC-20 0 to 70 100 Lead MQFP Q100.14x20 HSP43891VC-25 0 to 70 100 Lead MQFP Q100.14x20 HSP43891VC-30 0 to 70 100 Lead MQFP Q100.14x20 HSP43891JC-20 0 to 70 84 Lead PLCC N84.1.15 HSP43891JC-25 0 to 70 84 Lead PLCC N84.1.15 HSP43891JC-30 0 to 70 84 Lead PLCC N84.1.15 HSP43891GC-20 0 to 70 85 Pin CPGA G85.A HSP43891GC-25 0 to 70 85 Pin CPGA G85.A HSP43891GC-30 0 to 70 85 Pin CPGA G85.A CIN0 - 8 DF FILTER CELL 7 COUT0 - 8 ERASE DCM0 - 1 DIENB CIENB COENB MUX RESET 26 ADR0, ADR1, ADR2 CLK RESET SHADD SENBH SENBL OUTPUT STAGE VCC VSS DIN0 - DIN8 SUM0 - 25 3 9 DF FILTER CELL 6 26 9 DF FILTER CELL 5 26 9 DF FILTER CELL 4 26 9 DF FILTER CELL 3 26 9 DF FILTER CELL 2 26 9 DF FILTER CELL 1 26 9 DF FILTER CELL 0 26 9 9 5 5 2 26 26 2 9 5 CLK ADRO - 2 Data Sheet May 1999 |
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Similar Description - HSP43891VC-25 |
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