4

Pin Descriptions

SYMBOL

PLCC PIN NUMBER

TYPE

DESCRIPTION

16, 33, 63

The +5V power supply pin.

GND

14, 35, 55, 70, 77

Ground.

DIN0-7

17-24

I

The DIN0-7 bus consists of eight single data input pins. The assignment of the active pins is

determined by the configuration. Data is loaded synchronous to the rising edge of CLK. DIN0

is the LSB.

DOUT0-7

60-62, 64-68

O

The DOUT0-7 bus is the data output of the correlation array. The format of the output is de-

pendent on the window configuration and bit weighting. DOUT0 is the LSB.

CLK

15

I

System Clock. Positive edge triggered.

CASIN0-12

1-13

I

CASIN0-12 allows multiple correlators to be cascaded by connecting CASOUT0-12 of one

correlator to CASIN0-12 of another. The CASIN bus is added internally to the correlation

score to form CASOUT. CASIN0 is the LSB.

CASOUT0-12

69, 71-76, 78-83

O

CASOUT0-12 is the output correlation score. This value is the delayed sum of all the 256

taps of one chip and CASIN0-12. When the part is configured to act as two independent cor-

relators, CASOUT0-8 represents the correlation score for the first correlator while the sec-

ond correlation score is available on the AUXOUT0-8 bus. In this configuration, the

cascading feature is no longer an option. CASOUT0 is the LSB.

OEC

84

I

OEC is the output enable for CASOUT0-12. When OEC is high, the output is three-stated.

Processing is not interrupted by this pin (active low).

TXFR

36

I

TXFR is a synchronous clock enable signal that allows the loading of the reference and mask

inputs from the preload register to the correlation array. Data is transferred on the rising edge

of CLK while TXFR is low (active low).

DREF0-7

25-32

I

DREF0-7 is an 8-bit wide data reference input. This is the input data bus used to load the

reference data. RLOAD going active initiates the loading of the reference registers. This in-

put bus is used to load the reference registers of the correlation array. The manner in which

the reference data is loaded is determined by the window configuration. If the window con-

figuration is 1 x 256, the reference bits are loaded one at a time over DREF7. When the

HSP45256 is configured as an8x32array,the data is loaded into all stages in parallel. In

this case, DREF7 is the reference data for the first stage and DREF0 is the reference data

for the eighth stage. The contents of the reference data registers are not affected by chang-

ing the window configuration. DREF0 is the LSB.

RLOAD

34

I

RLOAD enables loading of the reference registers. Data on DREF0-7 is loaded into the pre-

load registers on the rising edge of RLOAD. This data is transferred into the correlation array

by TXFR (active low).

DCONT0-7

41-48

I

DCONT0-7 is the control data input which is used to load the mask bit for each tap, as well

as the configuration registers. The mask data is sequentially loaded into the eight stages in

the same manner as the reference data. DCONT0 is the LSB.

CLOAD

37

I

CLOAD enables the loading of the data on DCONT0-7. The destination of this data is con-

trolled by A0-2 (active low).

A0-2

38-40

I

A0-2 is a 3-bit address that determines what function will be performed when CLOAD is ac-

tive. This address bus is set up with respect to the rising edge of the load signal, CLOAD. A0

is the LSB.

AUXOUT0-8

50-54, 56-59

O

AUXOUT0-8 is a 9-bit bus that provides either the data reference output in the single corre-

lation configuration or the 9-bit correlation score of the second correlator, in the dual corre-

lator configuration. When the user programs the chip to be two separate correlators, the

score of the second correlator is output on this bus. When the user has programmed the chip

to be one correlator, AUXOUT0-7 represents the reference data out, with the state of

AUXOUT8 undefined. AUXOUT0 is the LSB.

OEA

49

I

The OEA signal is the output enable for the AUXOUT0-8 output. When OEA is high, the out-

put is disabled. Processing is not interrupted by this pin (active low).

HSP45256