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HSP45256

Binary Correlator

The Intersil HSP45256 is a high-speed, 256 tap binary

correlator. It can be configured to perform one-dimensional

or two-dimensional correlations of selectable data precision

and length. Multiple HSP45256’s can be cascaded for

increased correlation length. Unused taps can be masked

out for reduced correlation length.

The correlation array consists of eight 32-tap stages. These

may be cascaded internally to compare 1, 2, 4 or 8-bit input

data with a 1-bit reference. Depending on the number of bits

in the input data, the length of the correlation can be up to

256, 128, 64, or 32 taps. The HSP45256 can also be

configured as two separate correlators with window sizes

from 4 by 32 to 1 by 128 each. The mask register can be

used to prevent any subset of the 256 bits from contributing

to the correlation score.

The output of the correlation array (correlation score) feeds

the weight and sum logic, which gives added flexibility to the

data format. In addition, an offset register is provided so that

a preprogrammed value can be added to the correlation

score. This result is then passed through a user

programmable delay stage to the cascade summer. The

delay stage simplifies the cascading of multiple correlators

by compensating for the latency of previous correlators.

The Binary Correlator is configured by writing a set of control

registers via a standard microprocessor interface. To simplify

operation, both the control and reference registers are

double buffered. This allows the user to load new mask and

reference data while the current correlation is in progress.

Features

• Reconfigurable 256 Stage Binary Correlator

• 1-Bit Reference x 1, 2, 4, or 8-Bit Data

• Separate Control and Reference Interfaces

• 25.6, 33MHz Versions

• Configurable for 1-D and 2-D Operation

• Double Buffered Mask and Reference

• Programmable Output Delay

• Cascadable

• Standard Microprocessor Interface

Applications

• Radar/Sonar

• Spread Spectrum Communications

• Pattern/Character Recognition

- Error Correction Coding

Block Diagram

Ordering Information

PART NUMBER

TEMP.

PACKAGE

PKG.

NO.

HSP45256JC-25

0 to 70

84 Ld PLCC

N84.1.15

HSP45256JC-33

0 to 70

84 Ld PLCC

N84.1.15

HSP45256GC-25

0 to 70

85 Ld PGA

G85.A

HSP45256GC-33

0 to 70

85 Ld PGA

G85.A

HSP45256JI-25

-40 to 85

84 Ld PLCC

N84.1.15

HSP45256JI-33

-40 to 85

84 Ld PLCC

N84.1.15

256 TAP

CORRELATION

ARRAY

CONTROL

WEIGHT

AND SUM

MUX

DELAY

CASCADE

SUMMER

DIN0-7

DREF0-7

DCONT0-7

A0-2

CASIN0-12

AUXOUT0-8

CASOUT0-12

DOUT0-7

DOUT

DREFOUT

CSCORE

Data Sheet

May 1999

File Number

2814.4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207