1

File Number

2459.5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

HSP48901

3 x 3 Image Filter

The Intersil HSP48901 is a high speed 9-Tap FIR Filter

which utilizes 8-bit wide data and coefficients. It can be

configured as a one dimensional (1-D) 9-Tap filter for a

variety of signal processing applications, or as a two

dimensional (2-D) filter for image processing. In the 2-D

configuration, the device is ideally suited for implementing 3

x 3 kernel convolution. The 30MHz clock rate allows a large

number of image sizes to be processed within the required

frame time for real-time video.

Data is provided to the HSP48901 through the use of

programmable data buffers such as the HSP9500 or any

other Programmable Shift Register. Coefficient and pixel

input data are 8-bit signed or unsigned integers, and the

20-bit extended output guarantees no overflow will occur

during the filtering operation.

There are two internal register banks for storing independent

3 x 3 filter kernels, thus, facilitating the implementation of

adaptive filters and multiple filter operations on the same

data.

The configuration of the HSP48901 Image Filter is controlled

through a standard microprocessor interface and all inputs

and outputs are TTL compatible.

Features

• DC to 30MHz Clock Rate

• Configurable for 1-D and 2-D Correlation/Convolution

• Dual Coefficient Mask Registers, Switchable in a Single

Clock Cycle

• Two’s Complement or Unsigned 8-Bit Input Data and

Coefficients

• 20-Bit Extended Precision Output

• Standard

µP Interface

Applications

• Image Filtering

• Edge Detection/Enhancement

• Pattern Matching

• Real Time Video Filters

Block Diagram

Ordering Information

PART NUMBER

TEMP.

PACKAGE

PKG.

NO.

HSP48901JC-20

0 to 70

68 Ld PLCC

N68.95

HSP48901JC-30

0 to 70

68 Ld PLCC

N68.95

HSP48901GC-20

0 to 70

68 Ld PGA

G68.A

HSP48901GC-30

0 to 70

68 Ld PGA

G68.A

2:1

2:1

ADDRESS

DECODER

CONTROL

LOGIC

CLOCK

GEN

CLK

HOLD

3

CIN0-7

DIN1 (0-7)

DIN2 (0-7)

DIN3 (0-7)

A0-2

FRAME

LD

A

B

C

D

E

F

G

H

I

DOUT 0-19

CLOCK

INTERNAL

MODE

MODE

+

+

+

+

Data Sheet

May 1999