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HSP50016JC-75 Datasheet(PDF) 7 Page - Intersil Corporation |
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HSP50016JC-75 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 31 page 3-204 Phase Increment Register is added to the 24 LSBs of the output of the Phase Increment Register. On the next CLK, that sum is stored back in the Phase Increment Register, the new phase is stored in the Phase Register and the process is repeated. The phase increment is allowed to grow until the next phase increment would equal or exceed the maximum phase increment value. When this happens, the Phase Increment Register is reset to the minimum phase increment and the cycle starts over again. NOTE: The phase increment is never equal to the maximum phase increment, since the Phase Increment Register is reloaded if the next phase increment value would be greater than the maximum phase increment. From the time the Phase Generator starts at the minimum phase increment until it reaches the maximum phase increment, the phase word on clock n is given by: An example of the outputs of the Phase Increment Register, Phase Register, and the I output of the SIN/COS Generator are shown in Figure 4B. In Down Chirp Mode the local oscillator generates a signal with a linearly decreasing frequency (Figure 5A). The maximum phase increment is loaded into the Phase Increment Register and the phase offset value goes into the Phase Register. The delta phase increment is subtracted from the 24 LSBs of the phase increment to form a new phase increment at each clock. The phase increment is allowed to diminish until it reaches the minimum phase increment value, then it is reset to the maximum phase increment value and the cycle is repeated. Note that the value of the phase increment can be equal to, but never less than the minimum phase increment, since the Phase Increment Register is reloaded if the next phase increment value would be less than the minimum phase increment. This feature protects the DDC from exceeding the Nyquist frequency. In this case, from the time the Phase Generator starts at the maximum phase increment until it reaches the minimum phase increment, the phase word on clock n is given by: See Figure 5B for a graphical representation of this process. Phase Word Phase Offset - Minimum Phase Increment n (Delta Phase Increment) + [ ] = (EQ. 2) Phase Word Phase Offset -[Minimum Phase Increment n (Delta Phase Increment)] – = (EQ. 3) FIGURE 4A. PHASE WORD DURING UP CHIRP FIGURE 4B. UP CHIRP STARTING PHASE +90o ±180o -90o θ INCR θ INCR + θ ∆ 0o (0) (1) (2) (3) (4) (5) θ OFFSET θ INCR +2θ ∆ θ INCR +3θ ∆ θ INCR +4θ ∆ θ INCR (6) θ INCR + θ ∆ (7) θ INCR +2θ ∆ START NEW RAMP θ INCR +5θ ∆ > θMAX INCR (8) IF THEN MAXIMUM MINIMUM PHASE INCREMENT TIME PHASE PHASE WORD TIME COSINE OUTPUT OF SIN/COS GENERATOR TIME OFFSET HSP50016 |
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