 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
W632GU6KB-11 Datasheet(PDF) 5 Page - Winbond |
|
||||||||||||||||||||||||||||||
W632GU6KB-11 Datasheet(HTML) 5 Page - Winbond |
|
|
5 / 160 page  W632GU6KB Publication Release Date: Jan. 20, 2015 Revision: A06 - 5 - 1. GENERAL DESCRIPTION The W632GU6KB is a 2G bits DDR3L SDRAM, organized as 16,777,216 words 8 banks 16 bits. This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3L-1866) for various applications. The W632GU6KB is sorted into the following speed grades: -11, -12, 12I, -15 and 15I. The -11 speed grade is compliant to the DDR3L-1866 (13-13-13) specification. The -12 and 12I speed grades are compliant to the DDR3L-1600 (11-11-11) specification (the 12I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -15 and 15I speed grades are compliant to the DDR3L-1333 (9-9-9) specification (the 15I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The W632GU6KB is designed to comply with the following key DDR3L SDRAM features such as posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and asynchronous reset. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous fashion. 2. FEATURES Power Supply: 1.35V (typ.), VDD, VDDQ = 1.283V to 1.45V Backward compatible to VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 6, 7, 8, 9, 10, 11 and 13 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On- The-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data Edge-aligned with read data and center-aligned with write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CK and CK#) Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate) Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiency Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) Auto-precharge operation for read and write bursts Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR) Precharged Power Down and Active Power Down Data masks (DM) for write data Programmable CAS Write Latency (CWL) per operating frequency Write Latency WL = AL + CWL Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence |
Similar Part No. - W632GU6KB-11 |
|
Similar Description - W632GU6KB-11 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
