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ICL8052ACDD Datasheet(PDF) 16 Page - Intersil Corporation |
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ICL8052ACDD Datasheet(HTML) 16 Page - Intersil Corporation |
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16 / 21 page  5-21 Run/Hold Input When the Run/Hold input is connected to V+ or left open (this input has pullup resistor to ensure a high level when the pin is left open), the circuit will continuously perform conversion cycles, updating the output latches at the end of every Deintegrate (Phase III) portion of the conversion cycle (See Figure 8). (See under “Handshake Mode” for exception.) In this mode of operation, the conversion cycle will be performed in 131,072 for 7104-16 and 32768 for 7104-14 clock periods, regardless of the resulting value. If Run/Hold goes low at any time during Deintegrate (Phase III) after the zero crossing has occurred, the circuit will immediately terminate Deintegrate and jump to Auto-Zero. This feature can be used to eliminate the time spent in Deintegrate after the zero-crossing. If Run/Hold stays or goes low, the converter will ensure a minimum Auto-Zero time, and then wait in Auto-Zero until the Run/Hold input goes high. The converter will begin the Integrate (Phase II) portion of the next conversion (and the STATUS output will go high) seven clock periods after the high level is detected at Run/Hold. See Figure 10 for details. Using the Run/Hold input in this manner allows an easy “convert on demand” interface to be used. The converter may be held at idle in Auto-Zero with Run/Hold low. When Run/Hold goes high the conversion is started, and when the STATUS output goes low the new data is valid (or trans- ferred) to the UART - see Handshake Mode). Run/Hold may now go low terminating Deintegrate and ensuring a minimum Auto-Zero time before stopping to wait for the next conversion. Alternately, Run/Hold can be used to minimize conversion time by ensuring that it goes low during Deinte- grate, after zero crossing, and goes high after the hold point is reached. The required activity on the Run/Hold input can be provided by connecting it to the CLOCK3 (-14), CLOCK2 (-16) Output. In this mode the conversion time is dependent on the input value measured. Also refer to Intersil Application Bulletin A030 for a discussion of the effects this will have on Auto-Zero performance. If the Run/Hold input goes low and stays low during Auto- Zero (Phase I), the converter will simply stop at the end of the Auto-Zero and wait for Run/Hold to go high. As above, Integrate (Phase II) begins seven clock periods after the high level is detected. Direct Mode When the MODE pin is left at a low level, the data outputs [bits 1 through 8 low order byte, See Table 3 for format of middle (-16) and high order bytes] are accessible under control of the byte and CHIP ENABLE terminals as inputs. These ENABLE inputs are all active low, and are provided with pullup resistors to ensure an inactive high level when left open. When the CHIP ENABLE input is low, taking a byte ENABLE input low will allow the outputs of that byte to become active (three-stated on). This allows a variety of parallel data accessing techniques to be used. The timing requirements for these outputs are shown under AC Specifications and Table 1. It should be noted that these control inputs are asynchro- nous with respect to the converter clock - the data may be accessed at any time. Thus it is possible to access the data while it is being updated, which could lead to scrambled data. Synchronizing the access of data with the conversion cycle by monitoring the STATUS output will prevent this. Data is never updated while STATUS is low. Also note the potential bus conflict described under “Initial Clear Circuitry”. Handshake Mode The handshake output mode is provided as an alternative means of interfacing the ICL7104 to digital systems, where the A/D converter becomes active in controlling the flow of data instead of passively responding to chip and byte ENABLE inputs. This mode is specifically designed to allow a direct interface between the ICL7104 and industry-stan- dard UARTs (such as the Intersil CMOS UARTs, IM6402/3) with no external logic required. When triggered into the handshake mode, the ICL7104 provides all the control and flag signals necessary to sequence the three (ICL7106-16) or two (ICL7104-14) bytes of data into the UART and initiate their transmission in serial form. This greatly eases the task and reduces the cost of designing remote data acquisition stations using serial data transmission to minimize the number of lines to the central controlling processor. FIGURE 10. RUN/HOLD OPERATION DEINT TERMINATED AT ZERO CROSSING STATIC IN HOLD STATE INT PHASE 7 COUNTS INTEGRATOR OUTPUT INTERNAL CLOCK INTERNAL LATCH STATUS OUTPUT RUN/HOLD INPUT DETECTION -14 7161 8185 -16 28665 32761 OPTION MIN MAX ICL8052/ICL7104, ICL8068/ICL7104 |
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