9-25

Timing Diagrams

FIGURE 1. ICM7231 INPUT TIMING DIAGRAM

FIGURE 2. ICM7232 ONE DIGIT INPUT TIMING DIAGRAM, WRITING BOTH ANNUNCIATORS

DO NOT CARE

CS

INPUT

DATA

ADDRESS

INPUT

ADDRESS

AND DATA

INPUTS VALID

ADDRESS

AND DATA

INPUTS VALID

DATA

CLOCK

INPUT

(PER BIT

OF DATA)

DATA

INPUT

WRITE

INPUT

RESETS SHIFT REGISTER

AND INPUT CONTROL

LOGIC WHEN DATA

ACCEPTED HIGH

DECODES AND STORES

DATA, RESETS SHIFT

REGISTER AND LOGIC

WHEN DATA ACCEPTED

IS LOW

DO NOT CARE

ELEVENTH CLOCK

WITH NO WRITE PULSE

RESETS SR + LOGIC

DATA

ACCEPTED

OUTPUT

1

2

3

8

9

10

AN2

DATA

VALID

BD0

DATA

VALID

A2

DATA

VALID

A3

DATA

VALID

A1

DATA

VALID

AN1

DATA

VALID

ICM7231, ICM7232