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ISL6125IR Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL6125IR Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 16 page 6 FN9005.4 June 10, 2005 previous GATE has reached ~VQP-1V. 160ms after the last GATE is at VQP the RESET# output will be deasserted. Once any UVLO is unsatisfied, RESET# is pulled low, SYSRST# is pulled low and all GATEs are simultaneously turned off. When ENABLE# is signaled high the D GATE will start to pull low and once below 0.6V the next GATE will then start to pull low and so on until all GATEs are at 0V. Unloaded, this turn off sequence will complete in <1ms. This variant offers a lower cost and size implementation as the external delay caps are not used. Since the delay caps are not used this IC can not delay the start of subsequent GATEs thus necessary stabilization or system house keeping need to be considered. The ISL6128 is a four channel device that groups the four channels into two groups of two channels each, as A, B and C, D. Each group having its own ENABLE# and RESET# I/IO pins. This requires all four UVLO and both ENABLE#s to be satisfied for sequencing to start. The A, B group will first turn on 10ms after the second ENABLE# is pulled low with A then B turning on followed by C then D. Once the preceding GATE = VQP the next DLY_ON pin starts to charge its capacitor thus turning on all four GATEs. Approximately 160ms after D GATE = VQP the RESET# output is released to go high. Once any UVLO is unsatisfied, only the related group’s RESET# and two GATEs are pulled low. The related EN input has to be cycled for the faulted group to be turned-on again. Normal shutdown is invoked by either signaling both ENABLE# inputs high which will cause all the two related GATEs to shutdown in reverse order from turn-on. DLY_X caps adjust the delay between GATES during turn on and off but not the order. During bias up the RESET# output is guaranteed to be in the correct state with VDD lower than 1V. The SYSRST# pin is a true I/O connection having both functions. As an input, if it is pulled low all GATEs will unconditionally shut off and RESET# pulls low, see Figure 6. This input can be used as a no wait enabling input, if all inputs (ENABLE & UVLO) are satisfied it does not wait through the ~10ms enable delay to initiate DLY_ON cap charging. It is also useful when multiple sequencers are implemented in a design needing simultaneous shutdown (kill switch) across all sequencers. As an output, after the on sequence is completed it will pull low after any UVLO is unsatisfied longer than TFIL and pull all other SYSRST# inputs low on common connection thus unconditionally shutting down all outputs across multiple sequencers. Except ISL6128 after a fault, restart of the turn on sequence is automatic once all requirements are met. This allows for no interaction between the sequencer and a controller IC if desired. The ENABLE & RESET# I/O do allow for a higher level of feedback and control if desired. The ISL6128 requires that the related ENABLE# be cycled for restart of its associated group GATEs. If no capacitors are connected between DLY_ON or DLY_OFF pins and ground then all such related GATEs start to turn on immediately after the 10ms (TUVLOdel) ENABLE stabilization time out has expired and the GATEs start to immediately turn off when ENABLE is asserted. If some of the rails are to be sequenced together, in order to eliminate the effect of capacitor variance on the timing and to reduce cost, a common capacitor can be connected to two or more DLY_ON or DLY_OFF pins. In this case multiply the capacitor value by the number of common DLY_X pins to retain the desired timing. Table 1 illustrates the nominal time delay from the start of charging to the 1.27V reference for various capacitor values on the DLY_X pins. This table does not include the 10ms of enable lock out delay during a start up sequence but represents the time from the end of the enable lock out delay to the start of GATE transition. There is no enable lock out delay for a sequence off, so this table illustrates the delay to GATE transition from a disable signal. Figure 2 illustrates the turn-on and Figure 3 the nominal turnoff timing diagram of the ISL6123 and ISL6124 product. The ISL6125 is similar except the open drains instead of GATE pins are pulled up to VDD. Note the delay and flexible sequencing possibilities. TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE TIME (s) Open 0.00006 100pF 0.00013 1000pF 0.0013 0.01 µF 0.013 0.1 µF0.13 1 µF1.3 10 µF13 NOTE: Nom. TDEL_SEQ = Cap (µF) * 1.3MΩ. ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 |
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