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ADSP-2186M Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-2186M Datasheet(HTML) 5 Page - Analog Devices |
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5 / 40 page  REV. 0 ADSP-2186M –5– external buses with bus request/grant signals ( BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-2186M to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSP-2186M can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two level- sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchro- nous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSP-2186M provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n pro- cessor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports The ADSP-2186M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2186M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User’s Manual. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. • SPORTs can use an external serial clock or generate their own serial clock internally. • SPORTs have independent framing for the receive and trans- mit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings. • SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law companding according to CCITT recommendation G.711. • SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. • SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. • SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time- division multiplexed, serial bitstream. • SPORT1 can be configured to have two external interrupts ( IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration. PIN DESCRIPTIONS The ADSP-2186M is available in a 100-lead LQFP package and a 144-Ball Mini-BGA package. In order to maintain maxi- mum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are soft- ware configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. |
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