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ISL6560 Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6560 Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 14 page 11 FN9011.3 ISL6560 MOSFET Selection and Considerations In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty factor (see the following equations). The conduction losses are the main component of power dissipation for the lower MOSFETs, Q2 and Q4 of Figure 10. Only the upper MOSFETs, Q1 and Q3 have significant switching losses, since the lower device turns on and off into near-zero voltage. The equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET’s body diode. The gate-charge losses are dissipated by the driver IC and don't heat the MOSFETs. However, large gate-charge increases the switching time, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heat sink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Figure 10 shows a schematic of the circuit developed from the proceeding computations. This circuit is implemented on the ISL6560/62 Evaluation Board. The next section will discuss PC board layout. PC Board Layout Considerations Like all high-current supplies where low-voltage control signals in the millivolt range must live with high voltage and high-current switching signals, PC board layout becomes crucial in obtaining a satisfactory supply. Figure 11 shows a simplified diagram of the critical areas of a PC board layout. This diagram and the following material represent goals to work towards during the layout phase. Goals will be compromised during the layout process due to component placement and space constraints. The following text reviews these layout considerations in more detail. Current Sampling 1. Place the current sampling or sense resistor as close as possible to the upper MOSFET drains. This is important since the added inductance and resistance increase the impedance and result in a reduction in drain voltage during high peak pulse currents. P UPPER I O 2 r DS ON () × V OUT × V IN ------------------------------------------------------------ I O V IN × t SW × F S × 2 ---------------------------------------------------- + = P LOWER I O 2 r DS ON () × V IN V OUT – () × V IN --------------------------------------------------------------------------------- = 5m Ω HIP6601ECB +VCORE 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 PWRGD REF PWM1 PWM2 VCC CS- CS+ GND VID4 VID3 VID2 VID1 VID0 CT FB COMP 1 2 3 4 8 7 6 5 PHASE PVCC VCC LGATE UGATE BOOT PWM GND 1 2 3 4 8 7 6 5 PHASE PVCC VCC LGATE UGATE BOOT PWM GND { INPUT VID CODES from PROCSSOR +VIN 12V HIP6601ECB ISL6560 { 22k 15k 1k 10 Ω 20 Ω 330 Ω 4.3k 6 - 470 µF 2 - 4.7 µF 1nF 150pF 4.7 µF 330pF 15nF 0.1 µF 1 µF 100pF 0.1 µF 1 µF 1nF 6 - 1200 µF 16 - 22 µF 900nH 900nH C41-42 C15, C17-18, C29, C50-51 R13 R14 R6 C10 C11 R11 R12 R5 C13 C14 R7 C1 C2 C3 C4 L1 L2 C19, C30, C34-37, C39, C45-49, C60-63 C21, C24-28 L3 1 µH C20 C40 R27 C12 Q2 HUF76145 Q3 Q4 Q1 HUF76139 HUF76139 HUF76145 FIGURE 10. SCHEMATIC DIAGRAM OF A 40A SUPPLY USING THE ISL6560 CONTROLLER AND HIP6601 GATE DRIVERS |
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