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ISL6560 Datasheet(PDF) 2 Page - Intersil Corporation |
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ISL6560 Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 14 page 2 FN9011.3 Block Diagram Simplified Power System Diagram Functional Pin Description VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4) and VID0 (Pin 5) Voltage Identification inputs from microprocessor. These pins respond to TTL and 3.3V logic signals. The ISL6560 decodes VID bits to establish the output voltage. See Table 1. COMP (Pin 6) Output of the internal transconductance error amplifier. Voltage at this pin sets the output current level of the current sense comparator. Pulling this pin to ground disables the oscillator and drives both PWM outputs low. FB (Pin 7) Inverting input of the internal transconductance error amplifier. CT (Pin 8) A capacitor on this pin sets the frequency of the internal oscillator. GND (Pin 9) All signals are referenced to this bias and reference ground pin. PWRGD (Pin 10) This pin is an internal open drain connection. A high voltage level at this pin with a resistor connected to this pin and VCC indicates that CORE voltage is at the proper level, CS+ (Pin 11) and CS- (Pin 14) These inputs monitor the supply current to the upper MOSFETs. CS+ is connected directly to the decoupled supply voltage and current sensing resistor. CS- is connected to the other end of the current sensing resistor and the upper MOSFET drains. PWM2 (Pin 12) and PWM1 (Pin 13) PWM outputs that are connected to the gate driver ICs. REF (Pin 15) Three volt supply used to bias the output of the transconductance amplifier. VCC (Pin 16) Connect this bias supply pin to a 12V supply. D/A UV OVP E/A CMP PWM1 PWM2 CS+ CS- GND REF VCC FB VID4 VID3 VID2 VID1 VID0 COMP OSCILLATOR X1.24 PWRGD 3V REFERENCE BIAS CIRCUITS UVLO and CT CONTROL LOGIC + - + - + - X 0.82 + - SYNCHRONOUS ISL6560 MICROPROCESSOR FB VID RECTIFIED BUCK CHANNEL SYNCHRONOUS RECTIFIED BUCK CHANNEL PWM 1 PWM 2 VID4 VID3 VID2 VID1 VID0 CT PWRGD REF PWM1 PWM2 VCC FB CS- COMP CS+ GND 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 ISL6560 |
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