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ISL6843 Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL6843 Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 9 page 5 Gain, ACS = ∆VCOMP/∆VCS 0 < VCS < 910mV, VFB = 0V (Note 5) 2.5 3.0 3.5 V/V CS to OUT Delay (Note 5) - 25 40 nS ERROR AMPLIFIER Open Loop Voltage Gain (Note 5) 60 90 - dB Unity Gain Bandwidth (Note 5) 3.5 5 - MHz Reference Voltage VFB = VCOMP 2.475 2.500 2.525 V FB Input Bias Current VFB = 0V -1.0 -0.2 1.0 µA COMP Sink Current VCOMP = 1.5V, VFB = 2.7V 1.0 - - mA COMP Source Current VCOMP = 1.5V, VFB = 2.3V -0.4 - - mA COMP VOH VFB = 2.3V 4.80 - VREF V COMP VOL VFB = 2.7V 0.4 - 1.0 V PSRR Frequency = 120Hz, VDD = 12V to 18V (Note 5) 60 80 - dB OSCILLATOR Frequency Accuracy Initial, TJ = 25 oC 495255 kHz Frequency Variation with VDD T = 25oC (F18V - F12V)/F12V -0.2 1.0 % Temperature Stability (Note 5) - - 5 % Amplitude, Peak to Peak -1.9 - V RTCT Discharge Voltage - 0.7 - V Discharge Current RTCT = 2.0V 7.2 8.4 9.5 mA OUTPUT Gate VOH VDD - OUT, IOUT = -200mA - 1.0 2.0 V Gate VOL OUT - GND, IOUT = 200mA - 1.0 2.0 V Peak Output Current COUT = 1nF (Note 5) - 1.0 - A Rise Time COUT = 1nF (Note 5) - 20 40 nS Fall Time COUT = 1nF (Note 5) - 20 40 nS PWM Maximum Duty Cycle ISL6842, ISL6843 94 96 - % ISL6844, ISL6845 47 48 - % Minimum Duty Cycle ISL6842, ISL6843 - - 0 % ISL6844, ISL6845 - - 0 % NOTES: 3. Specifications at -40oC are guaranteed by design, not production tested. 4. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 5. Guaranteed by design, not 100% tested in production. 6. Adjust VDD above the start threshold and then lower to 15V. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. VDD = 15V (Note 6), Rt = 10kΩ, Ct = 3.3nF, TA = -40 to 105 oC (Note 3), Typical values are at TA = 25 oC (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ISL6842, ISL6843, ISL6844, ISL6845 |
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Similar Description - ISL6843 |
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