ADT7318_15 datasheet(5/44 Pages) AD

Part #	ADT7318

Description	0.5C Accurate Digital Temperature Sensor and Quad Voltage Output 12-/10-/8-Bit DACs

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ADT7316/ADT7317/ADT7318

Rev. B | Page 5 of 44

Parameter1

Min

Typ

Max

Unit

Conditions/Comments

DIGITAL OUTPUT

Output High Voltage, VOH

2.4

V

ISOURCE = ISINK = 200 μA.

Output Low Voltage, VOL

0.4

V

IOL = 3 mA.

Output High Current, IOH

1

mA

VOH = 5 V.

Output Capacitance, COUT

50

pF

INT/INT Output Saturation Voltage

0.8

V

IOUT = 4 mA.

I2C TIMING CHARACTERISTICS7, 8

Serial Clock Period, t1

2.5

μs

Fast-mode I2C. See

Figure 4.

Data In Setup Time to SCL High, t2

50

ns

Data Out Stable After SCL Low, t3

0

ns

See

Figure 4.

SDA Low Setup Time to SCL Low

(Start Condition), t4

50

ns

See

Figure 4.

SDA High Hold Time After SCL High

(Stop Condition), t5

50

ns

See

Figure 4.

SDA and SCL Fall Time, t6

300

ns

See

Figure 4.

SDA and SCL Rise Time, t6

3009

ns

See

Figure 4.

SPI TIMING CHARACTERISTICS10, 11

CS to SCLK Setup Time, t1

0

ns

See

Figure 7.

SCLK High Pulse Width, t2

50

ns

See

Figure 7.

SCLK Low Pulse Width, t3

50

ns

See

Figure 7.

Data Access Time After SCLK Falling

Edge, t412

35

ns

See

Figure 7.

Data Setup Time Prior to SCLK

Rising Edge, t5

20

ns

See

Figure 7.

Data Hold Time after SCLK Rising

Edge, t6

0

ns

See

Figure 7.

CS to SCLK Hold Time, t7

0

ns

See

Figure 7.

CS to DOUT High Impedance, t8

40

ns

See

Figure 7.

POWER REQUIREMENTS

VDD

2.7

5.5

V

VDD Settling Time

50

ms

VDD settles to within 10% of its final voltage level.

IDD (Normal Mode)13

3

mA

VDD = 3.3 V, VIH = VDD, and VIL = GND.

2.2

3

mA

VDD = 5 V, VIH = VDD , and VIL = GND.

IDD (Power-Down Mode)

10

μA

VDD = 3.3 V, VIH = VDD, and VIL = GND.

10

μA

VDD = 5 V, VIH = VDD, and VIL = GND.

Power Dissipation

10

mW

VDD = 3.3 V, using normal mode.

33

μW

VDD = 3.3 V, using shutdown mode.

1 See the Terminology section.

2 DC specifications tested with the outputs unloaded.

3 Linearity is tested using a reduced code range: ADT7316 (Code 115 to 4095); ADT7317 (Code 28 to 1023); ADT7318 (Code 8 to 255).

4 A round robin is the continuous sequential measurement of the following three channels: VDD, internal temperature, and external temperature.

5 Guaranteed by design and characterization, but not production tested.

6 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD, offset plus

gain error must be positive.

7 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate,

but has a negative effect on the EMC behavior of the part.

8 Guaranteed by design. Not tested in production.

9 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.

10 Guaranteed by design and characterization, but not production tested.

11 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

12 Measured with the load circuit of Figure 5.

13 IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

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