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ADUC7032-8L Datasheet(PDF) 7 Page - Analog Devices |
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ADUC7032-8L Datasheet(HTML) 7 Page - Analog Devices |
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7 / 120 page  ADuC7032-8L Rev. A | Page 7 of 120 Parameter Test Conditions/Comments Min Typ Max Unit LIN I/O GENERAL Baud Rate 1000 20,000 Bits/sec VDD Supply voltage range at which the LIN interface is functional 7 18 V Input Capacitance 5.5 pF LIN Comparator Response Time1 Using 22 Ω resistor 38 90 μs ILIN DOM MAX Current limit for driver when LIN bus is in dominant state; VBAT = VBAT(MAX) 40 200 mA ILIN_PAS_REC Driver off; 7.0 V < VBUS < 18 V; VDD = VLIN − 0.7 V −20 +20 μA ILIN_PAS_DOM1 Input leakage VLIN = 0 V −1 mA ILIN_NO_GND30 Control unit disconnected from ground, GND = VDD; 0 V < VLIN < 18 V; VBAT = 12 V −1 +1 mA VLIN_DOM1 LIN receiver dominant state, VDD > 7.0 V 0.4 VDD V VLIN_REC1 LIN receiver recessive state, VDD > 7.0 V 0.6 VDD V VLIN_CNT1 LIN receiver center voltage, VDD > 7.0 V 0.475 VDD 0.5 VDD 0.525 VDD V VHYS1 LIN receiver hysteresis voltage 0.175 VDD V VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage; VDD = 7.0 V RL 500 Ω 1.2 V RL 1000 Ω 0.6 V VLIN_DOM_DRV_HISUP1 LIN dominant output voltage; VDD = 18 V RL 500 Ω 2 V RL 1000 Ω 0.8 V VLIN_RECESSIVE LIN recessive output voltage 0.8 VDD V VBAT Shift30 0 0.1 VDD V GND Shift30 0 0.1 VDD V RSLAVE Slave termination resistance 20 29 47 kΩ VSERIAL DIODE30 Voltage drop at the serial diode, DSer_Int 0.4 0.7 1 V Transmit Propagation Delay1 VDDMIN = 7 V 4 μs Bus load conditions (CBUS ||RBUS): 1 nF ||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω Symmetry of Transmit Propagation Delay1 VDDMIN = 7 V −2 +2 μs Receive Propagation Delay1 VDDMIN = 7 V 6 μs Symmetry of Receive Propagation Delay1 VDDMIN = 7 V −2 +2 μs LIN v.1.3 SPECIFICATION Bus load conditions (CBUS ||RBUS): 1 nF ||1 kΩ ; 6.8 nF||660 Ω; 10 nF||500 Ω Slew rate dt dV 1 Dominant and recessive edges, VBAT = 18 V 1 2 3 V/μs Slew rate dt dV 1 Dominant and recessive edges, VBAT = 7 V 0.5 3 V/μs tSYM1 Symmetry of rising and falling edge, VBAT = 18 V −5 +5 μs Symmetry of rising and falling edge, VBAT = 7 V −4 +4 μs LIN 2.0 SPECIFICATION Bus load conditions ( CBUS ||RBUS ): 1 nF ||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω D1 Duty Cycle 1 0.396 THREC(MAX) = 0.744 × VBAT, THDOM(MAX) = 0.581 × VBAT, VSUP = 7.0 V…18 V; tBIT = 50 μs, D1 = tBUS_REC(MIN)/(2 × tBIT) D2 Duty Cycle 2 THREC(MIN) = 0.284 × VBAT, THDOM(MIN) = 0.422 × VBAT, VSUP = 7.0 V…18 V; tBIT = 50 μs, D2 = tBUS_REC(MAX)/(2 × tBIT ) 0.581 |
Similar Part No. - ADUC7032-8L_15 |
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Similar Description - ADUC7032-8L_15 |
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