REV. B

OP37

–5–

Wafer Test Limits

OP37NT

OP37N

OP37GT

OP37G

OP37GR

Parameter

Symbol

Conditions

Limit

Limit

Limit

Limit

Limit

Unit

Input Offset

Voltage

Note 1

60

35

200

60

100

mV MAX

Input Offset

Current

50

35

85

50

75

nA MAX

Input Bias

Current

±60

±40

±95

±55

±80

nA MAX

Input Voltage

Range

IVR

±10.3

±11

±10.3

±11

±11

V MIN

Common Mode

Rejection Ratio

CMRR

±11 V 108

114

100

106

100

dB MIN

Power Supply

Rejection Ratio

PSRR

∞C,

±4 V to

±18 V

10

10

1010

20

mV/V MAX

∞C,

±4.5 V to

±18 V

16

20

mV/V MAX

Large-Signal

Voltage Gain

≥ 2 kW,

±10 V

600

1000

500

1000

700

V/mV MIN

≥ 1 kW,

±10 V

800

800

V/mV MIN

Output Voltage

Swing

≥ 2 kW±11.5

±12

±11

±12

±11.5

V MIN

≥ 600 kW±10

±10

±10

V MIN

Power

Consumption

140

140

170

mW MAX

NOTES

For 25

∞C characterlstics of OP37NT and OP37GT devices, see OP37N and OP37G characteristics, respectively.

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

unless otherwise noted.)

BINDING DIAGRAM

1

2

3

4

6

8

7

1427U

1990

1. NULL

2. (–) INPUT

3. (+) INPUT

4. V–

6. OUTPUT

7. V+

8. NULL