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DAC39J82 Datasheet(PDF) 4 Page - Texas Instruments |
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DAC39J82 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 144 page  DAC39J82 SLASE47 – JANUARY 2015 www.ti.com Pin Functions PIN I/O DESCRIPTION NAME NUMBER CMOS output for ALARM condition. The ALARM output functionality is defined through the ALARM L8 O config7 register. Default polarity is active high, but can be changed to active high via config0 alarm_out_pol control bit. If not used it can be left open. AMUX0 H3 I/O Analog test pin for SerDes, Lane 0 to Lane 3. It can be left open if not used. AMUX1 E3 I/O Analog test pin for SerDes, Lane 4 to Lane 7. It can be left open if not used. ATEST K9 I/O Analog test pin for DAC, references and PLL. It can be left open if not used. Positive LVPECL clock input for DAC core with Vcm = 0.5V. It can be PLL reference clock or DACCLKP A10 I external DAC sampling rate clock. If not used, DACCLK is self-biased with 100mV differential at Vcm = 0.5V. DACCLKN A9 I Complementary LVPECL clock input for DAC core. (see the DACCLKP description) Used as external reference input when internal reference is disabled through config27 extref_ena = ‘1’. Used as internal reference output when config27 extref_ena = ‘0’ (default). EXTIO F10 I/O Requires a 0.1 μF decoupling capacitor to analog GND when used as reference output. It can be left open if not used. A12, F12, G12, M12, A11, B11, C11, D11, E11, F11, G11, H11, J11, K11, L11, M11, C8, D8, E8, F8, G8, H8, J8, GND I These pins are ground for all supplies. E7, F7, G7, H7, E6, F6, G6, H6, A5, B5, E5, F5, G5, H5, A4, B4, M4, B3, C3, L3, B2, C2, D2, E2, H2, J2, K2, L2 IFORCE C5 I/O Analog test pin for on chip parametric. It can be left open if not used. IOUTAP B12 O A-Channel DAC current output. Must be tied to GND if not used. IOUTAN C12 O A-Channel DAC complementary current output. Must be tied to GND if not used. IOUTBP E12 O B-Channel DAC current output. Must be tied to GND if not used. IOUTBN D12 O B-Channel DAC complementary current output. Must be tied to GND if not used. IOUTCP H12 O C-Channel DAC current output. Must be tied to GND if not used. IOUTCN J12 O C-Channel DAC complementary current output. Must be tied to GND if not used. IOUTDP L12 O D-Channel DAC current output. Must be tied to GND if not used. IOUTDN K12 O D-Channel DAC complementary current output. Must tied to GND if not used. LPF C9 I/O External PLL loop filter connection. It can be left open if not used. Full-scale output current bias. Change the full-scale output current through coarse_dac(3:0). RBIAS G10 O Expected to be 1.92k Ω to GND. Active low input for chip RESET, which resets all the programming registers to their default RESETB K8 I state. Internal pull-up. It can be left open if not used. CML SerDes interface lane 0 input, positive, expected to be AC coupled. It can be left open if RX0P G1 I not used. CML SerDes interface lane 0 input, negative, expected to be AC coupled. It can be left open if RX0N H1 I not used. CML SerDes interface lane 1 input, positive, expected to be AC coupled. It can be left open if RX1P K1 I not used. CML SerDes interface lane 1 input, negative, expected to be AC coupled. It can be left open if RX1N J1 I not used. CML SerDes interface lane 2 input, positive, expected to be AC coupled. It can be left open if RX2P L1 I not used. CML SerDes interface lane 2 input, negative, expected to be AC coupled. It can be left open if RX2N M1 I not used. CML SerDes interface lane 3 input, positive, expected to be AC coupled. It can be left open if RX3P M3 I not used. 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DAC39J82 |
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