LT5502

6

APPLICATIO S I FOR ATIO

The LT5502 consists of the following sections: IF limiter,

I/Q demodulators, quadrature LO carrier generator, inte-

grated lowpass filters (LPFs), and bias circuitry.

An IF signal is fed to the inputs of the IF limiter. The limited

IF signal is then demodulated into I/Q baseband signals

using the quadrature LO carriers that are generated from

the divide-by-two circuit. The demodulated I/Q signals are

passed through 5th order LPFs and buffered with an

output driver.

IF Limiter

The IF limiter has 84dB small-signal gain with a frequency

range of 70MHz to 400MHz. It consists of two cascaded

stages of IF amplifiers/limiters. The differential outputs of

the first stage are connected internally to the differential

inputs of the second stage. An interstage filtering is

possible in between (Pin 12 and Pin 13) with minimum off-

chip components. It can be a simple parallel LC tank circuit

L1 and C8 as shown in Figure 3. The 22nF blocking

capacitor, C19, is used for the proper operation of the

internal DC offset canceling circuit. To achieve the best

receiver sensitivity, a differential configuration at the IF

input is recommended due to its better immunity to 2XLO

signal coupling to the IF limiter. Otherwise, the 2XLO

interference, presented at the IF inputs, may saturate the

IF limiter and reduce the gain of the wanted IF signal. The

receiver’s 3dB input-limiting sensitivity will be affected

correspondingly. The interstage bandpass filter will mini-

mize both 2XLO feedthrough and the receiver’s noise

bandwidth. Therefore, the receiver’s input sensitivity can

be improved. Without the interstage filter, the second

stage will be limited by the broadband noise amplified by

the first stage. The noise bandwidth in this case can be as

high as 500MHz. The 3dB input limiting sensitivity is about

–79dBm at an IF frequency of 280MHz when terminated

with 200

Ω at the input. The differential IF input impedance

is 2.2k

Ω. Therefore, a 240Ω resistor is used for R3 as

shown in Figure 3. Using a bandpass filter with 50MHz

bandwidth, the input sensitivity is improved to –86dBm.

The 1:4 IF input transformer can also be replaced with a

narrow band single-to-differential conversion circuit

using three discreet elements as shown in Figure 1. Their

nominal values are listed in Table 1. Due to the parasitics

of the PCB, their values need to be compensated. The

receiver’s input sensitivity in this case is improved to

–85dBm even without interstage filtering. The matching

circuit is essentially a second order bandpass filter. There-

fore, the requirement for the front-end channel-select

filter can be eased too.

Figure 1. IF Input Matching Network at 280MHz

Table 1. The Component Values of Matching Network

70

642

13.7

100

422

9.6

150

256

6.4

200

176

4.8

250

130

3.8

300

101

3.2

350

80.4

2.7

400

66.0

2.4

In an application where a lower input sensitivity is satisfac-

tory, one of the IF inputs can be simply AC-terminated with

a 50

Ω resistor and the other AC-grounded. The input

receiver’s sensitivity is about – 76dBm at 280MHz in this

case.

3.3pF

C5

22nF

3.3pF

120nH

IF

INPUT

5502 F01

MATCHING NETWORK