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AN2842 Datasheet(PDF) 5 Page - STMicroelectronics |
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AN2842 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 22 page AN2842 Approach to the study Doc ID 15110 Rev 1 5/22 2 Approach to the study To better understand the factors that cause current imbalance, it is important to divide the analysis into two different areas: in the first, we study the influence of the parameters around the power device, while in the second we analyze the impact of the intrinsic parameters of the power MOSFET. The parameters analyzed in the first approach are: ● differences between the power circuit components ● gate circuitry ● influence of the boost diode in the current imbalance ● temperature imbalance between devices In the second part, we analyze the parameters linked directly to the power MOSFET, and in particular: ● differences in the VGS(th) ● differences of RDS(on) ● influence of the gfs parameter 2.1 Differences between the power circuit components The primary contributors to current imbalance in power circuits are different drain or branch inductance and common source inductance. These "parasitic" inductances (labeled as Lp in Figure 4) are mainly generated by interconnection wiring and discrete components and have different effects depending on where they are situated. Thus the variation between branches is a function of layout symmetry and production tolerance. If we analyze a system that uses devices with similar electrical characteristics, the different device behaviors are linked to external parameters. Figure 4. Parasitic inductance in a circuit The impact due to the inductance in series to the gate terminal during the turn-on operation is a delay of the event. In fact, when the signal coming to the driver is applied to the gate, the inductance Lp in series generates an extra voltage that decreases the real voltage on the gate pin and consequently causes a delay of the operation. The same delay effects during turn-on are caused by the parasitic inductances on the drain and source pins. Also during turn-off operation, the impact due to the parasitic inductances is to generate a delay of the commutations. In the following figure, we can see how an external inductance introduced on the gate pin generates a delay on the drain current. |
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