Synchronous buck converter description

AN4150

6/20

Doc ID 023526 Rev 1

In these conditions, it is interesting to analyze the switching transients.

In Figure 2, the HS and LS waveforms during LS turn-off are reported. The top half of the

The main LS turn-on steps are analyzed in detail, as follows:

1.

source to drain (green trace). At the end of (1), the driver begins to turn off the FET.

2.

remove the charge stored in the device intrinsic capacitances. At the end of (2), the

current is dropped to low values (intrinsic caps are discharged) and the load current

diverts from the Power MOSFET channel to the body-drain diode.

3.

consequence, minority excess charge in both diode regions is created.

4.

The LS current decreases linearly, while the HS current increases linearly in direct

proportion to the fall of the LS FET current. To completely turn off the LS device, the

excess stored charge in its body diode must be removed: so, the reverse recovery

HS current peak is, therefore, given by:

The spurious bouncing on the LS gate signal is caused by the voltage drop across

package parasitic inductances (especially, source inductance), related to negative dl/dt

(the current is falling to zero). Obviously, the bigger the parasitic inductance (package,

wire bonding and layout) the higher the bouncing amplitude. At the same time, the low-

During device turn-off, the gate current is negative, because of the Power MOSFET intrinsic

capacitances discharge process. The current is sunk by the driver, with a speed linked to the

It is important to underline that, at LS turn-off, the driver, external and intrinsic FET gate

resistance should be as low as possible in order to minimize the device shoot-through risks,

caused by high dv/dt across drain-source, coupled to the gate signals through Miller

capacitance in Figure 3.