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LT1123 Datasheet(PDF) 9 Page - Linear Technology |
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LT1123 Datasheet(HTML) 9 Page - Linear Technology |
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9 / 16 page  9 LT1123 1123fb voltage and resistor value. Power dissipation can be calculated using the following formula: P V– V – V R RD IN BE DRIVE 2 = () where: VBE = emitter/base voltage of the PNP pass transistor VDRIVE = voltage at the drive pin of the LT1123 = VSAT of the drive pin in the worst case The worst-case power dissipation in the PNP pass transis- tor is simply equal to: PMAX = (VIN – VOUT)(IOUT) where VIN = Maximum VIN IOUT = Maximum IOUT The thermal resistance of the MJE1123 is equal to: 70 °C/W Junction to Ambient (no heat sink) 1.67 °C/W Junction to Case The PNP will normally be attached to either a chassis or a heat sink so the actual thermal resistance from junction to ambient will be the sum of the PNP’s junction to case thermal resistance and the thermal resistance of the heat sink or chassis. For nonstandard heat sinks the user will need to determine the thermal resistance by experiment. The maximum junction temperature rise above ambient for the PNP pass transistor will be equal to the maximum power dissipation times the thermal resistance, junction to ambient, of the PNP. The maximum operating junction temperature of the MJE1123 is 150 °C. The maximum operating ambient temperature for the MJE1123 will be equal to 150 °C minus the maximum junction temperature rise. The SOT-223 package is designed to be surface mounted. Heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. The thermal resistance from junction to ambient can be as low as 50 °C/W.ThisrequiresareasonablysizedPCboardwith at least one layer of copper to spread the heat across the board and couple it into the surrounding air. The table below can be used as a guideline in estimating thermal resistance. Data for the table was generated using 1/16" FR-4 board with 1oz copper foil. Table 1. Copper Area Thermal Resistance Topside* Backside Board Area (Junction to Ambient) 2500 sq. mm 2500 sq. mm 2500 sq. mm 50 °C/W 1000 sq. mm 2500 sq. mm 2500 sq. mm 50 °C/W 225 sq. mm 2500 sq. mm 2500 sq. mm 58 °C/W 100 sq. mm 2500 sq. mm 2500 sq. mm 64 °C/W 1000 sq. mm 1000 sq. mm 1000 sq. mm 57 °C/W 1000 sq. mm 0 1000 sq. mm 60 °C/W * Tab of device attached to topside copper For the LT1123 the tab is ground so that plated through holes can be used to couple the tab both electrically and thermally to the ground plane layer of the board. This will help to lower the thermal resistance. Thermal Limiting The thermal limit of the LT1123 can be used to protect both the LT1123 and the PNP pass transistor. This is accom- plished by thermally coupling the LT1123 to the power transistor. There are clip type heat sinks available for the TO-92 package that will allow the LT1123 to be mounted to the same heat sink as the PNP pass transistor. One example is manufactured by IERC (part #RUR67B1CB). The LT1123 should be mounted as close as possible to the Figure 8. Power in RD VIN (V) 6 8 1k LT1123 F08 10 100 715 14 13 12 11 10 9 5 1W 0.5W 0.25W 2W APPLICATIO S I FOR ATIO |
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