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AN394 - APPLICATION NOTE

This problem can be avoided by inserting a current limiting resistor in the current sink path. Figure 4 shows

some possible locations for this resistor. However, the best location is between the Q output and the D/Q

bus for the following reasons:

– During the overlap time, only the D driver is providing useful information. The Q driver simply outputs a

constant zero. By placing the resistor in this position, the D driver overrides the Q driver at setting the

logic level on the D/Q bus, thereby allowing the last address bit to be presented on the D pin for the

specified hold time (tDVCH).

– The R resistor slows down the propagation time of the Q output signals on the D/Q bus, as discussed

later in this document. In this position, the resistor only slows down the transmission of the 16 bits of

data during a READ operation. If R were in series with the D driver, all operations would be slowed

down.

Figure 4. Possible Locations for the Current Limiting Resistor

The R resistor does not have any effect as long as Q is in its high impedance state. During the execution

of a READ instruction, R sinks some current from the D driver during the short overlap time. Then the D

driver is disabled and Q output takes control of the D/Q bus through the R resistor.

Because of the bus capacitance, C, the signals are distorted, as shown in Figure 5 (on the next page): the

rising and falling edges of the Q output are transformed into exponential curves whose shape depends on

the time constant RC.

Ai02421

EEPROM Device

D

Q

A0="1"

Recommended

Location

D Driver

Output

Buffer

VCC

R

R

R

Not Recommended

Locations

(If D driver is an

open collector type)