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LT4321 Datasheet(PDF) 8 Page - Linear Technology

Part # LT4321
Description  PoE Ideal Diode Bridge Controller
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT4321 Datasheet(HTML) 8 Page - Linear Technology

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LT4321
8
4321f
For more information www.linear.com/LT4321
applicaTions inForMaTion
Transient Voltage Suppressor
The LT4321 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, pins that interface to Ethernet cables or remote
telecomsuppliescanroutinelyseeexcessivepeakvoltages.
To protect the LT4321, install a unidirectional transient
voltage suppressor (TVS) such as an SMAJ60A between
OUTP and OUTN. This TVS must be mounted as close as
possible to the LT4321.
For extremely high cable discharge and surge protection
contact Linear Technology Applications.
MOSFET Selection
Select external MOSFETs that have a drain-source break-
down voltage higher than the maximum input voltage.
For PoE systems the drain-source breakdown should be
at least 100V. For all applications the gate threshold must
be a minimum of 2V.
The amount of power saved by the LT4321 depends on the
channel resistance, RDS(ON), of the external MOSFETs. To
maximize performance and power savings select RDS(ON)
such that the forward voltage drop, VF, is between 20mV
and 70mV. Given the average output load current, IAVG:
RDS(ON) = VF/IAVG
For example, a PoE+ class 4 PD’s maximum average cur-
rent, IAVG, is 600mA. Choosing a MOSFET forward voltage
drop of 40mV reduces power consumption to 1/15th that
of a B2100 Schottky diode bridge.
RDS(ON) = 40mV/600mA = 66mΩ
Enable Pins
When OUTP is greater than VUVLO, the enable pins EN
and EN will control whether the LT4321 is in shutdown
mode or ideal bridge mode (Table 1 and Table 2). EN and
EN may be driven by a 3.3V or 5V logic signal, or with an
open drain or collector.
The EN pin is pulled up to the internally generated voltage
VENOC by an internal 250kΩ resistor. The EN pin is pulled
down to OUTN by an internal 250kΩ resistor. When OUTP
is less than 12V the enable pins are high impedance to
prevent these resistors from corrupting PoE detection.
The enable pins tolerate 100V (absolute maximum) and
may be tied directly to the OUTP or OUTN pins as needed.
Figure 3 and Figure 4 show how to interface the enable
pins to a PD interface controller. In these configurations,
the LT4321 PoE ideal bridge will be enabled after detec-
tion and classification are complete and before the PD is
consuming a significant amount of current.


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