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HD74LV2GT240A Datasheet(HTML) 9 Page - Renesas Technology Corp

Part No. HD74LV2GT240A
Description  Dual Bus Buffer Inverted with 3–state Output / CMOS Logic Level Shifter
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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HD74LV2GT240A Datasheet(HTML) 9 Page - Renesas Technology Corp

 
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HD74LV2GT240A
Rev.2.00, Oct.23.2003, page 7 of 8
tPLH
tPHL
VOH
VOL
GND
VI
VI
Vref
Vref
Vref
Vref
50%
50%
50%
50%
Input A
Output
Y
• Waveforms – 1
• Waveforms – 2
tf
10 %
10 %
90 %
90 %
tr
V
– 0.3 V
OH
V
+ 0.3 V
OL
tZL
tLZ
tZH
tHZ
VOH
VOL
Waveform – A
Input
OE
Waveform – B
GND
GND
VCC
tr
tf
10 %
10 %
90 %
90 %
Notes: 1. Input waveform : PRR
≤ 1 MHz, Zo = 50 Ω.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
VCC (V)
Vref
tr / tf
3.3±0.3
2.5 V
VI
INPUTS
50%
1.5 V
3 V
5.0±0.5
≤ 3.0 ns
≤ 3.0 ns


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