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AN2367 Datasheet(PDF) 3 Page - STMicroelectronics |
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AN2367 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 13 page AN2367 Background 3/13 1 Background 1.1 The problem In a TCP/IP application, the packets are transferred from the STR91x Ethernet MAC unit to STR91x on-chip memory using one of the STR91x DMA channels. Inside this packet will be a 14-byte header, which is the source of the misalignment. All following data will be misaligned by 2 bytes, making the processing of the packet by the CPU much slower. Figure 1. Data misalignment overview 1.2 The solution The solution is to have an optimized routine which will read the source buffer and write in the destination buffer with an offset of 2 bytes. Hence the data will now be fully aligned. Table 1. Memory copy example Before After Data starts at address 0x040001A8E (misaligned) 0x040001A8C (aligned) |
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