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HD74LV373ARPEL Datasheet(PDF) 3 Page - Renesas Technology Corp |
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HD74LV373ARPEL Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 13 page Rev.2.00 Jun. 25, 2004 page 1 of 10 HD74LV373A Octal D-type Transparent Latches with 3-state Outputs REJ03D0331–0200Z (Previous ADE-205-274 (Z)) Rev.2.00 Jun. 25, 2004 Description The HD74LV373A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • V CC = 2.0 V to 5.5 V operation • All inputs V IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • All outputs V O (Max.) = 5.5 V (@VCC = 0 V) • Typical V OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical V OH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) • Output current ±8 mA (@V CC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V) • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV373AFPEL SOP–20 pin (JEITA) FP–20DAV FP EL (2,000 pcs/reel) HD74LV373ARPEL SOP–20 pin (JEDEC) FP–20DBV RP EL (1,000 pcs/reel) HD74LV373ATELL TSSOP–20 pin TTP–20DAV T ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs OE LE D Output Q HX X Z LH L L LH H H LL X Q0 Note: H: High level L: Low level X: Immaterial Z: High impedance Q0: Output level before the indicated steady state input conditions were established. |
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