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M66591GP Datasheet(PDF) 5 Page - Renesas Technology Corp |
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M66591GP Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 135 page  M66591GP Rev .1.00 Nov . 30, 2004 page 3 of 131 The pin functions of the M66591 are shown in Table 1.1. Table 1.1 Pin Functions of M66591 Item Pin Name Input/Output Name / Function Pin Count CPU interface D15-D8 Input/Output Data Bus These are data bus to access the registers from the CPU. 8 D7/AD7-D1/AD 1, D0 Input/Output Data Bus / Address Bus When select to 16-bit separate bus, these pins are used as D7-D0 of data bus. When select to 16-bit multiplex bus, D7-D0 input/output and AD7-AD1 input are performed at time-sharing. In this case, AD0 is not used. 8 A7/ALE, A6-A1 Input Address Bus / Address Latch Enable When select to 16-bit separate bus, these pins are address bus to access the registers from the CPU. When select to 16-bit multiplex bus, A7 becomes the ALE pin, latching addresses at the falling edge. A6-A1 are not used. 7 CS_N Input Chip Select When this pin is low level, M66591 is selected. 1 RD_N Input Read Strobe Data are read from registers at low level. 1 WR1_N Input D15-D8 Byte Write Strobe The data (D15-D8) are written to the registers at the rising edge. 1 WR0_N Input D7-0 Byte Write Strobe The data (D7-D0) are written to the registers at the rising edge. 1 MPBUS Input Bus Mode Select The 16-bit separate bus is selected at low level. The 16-bit multiplex bus is selected at high level. This pin should not be switched after H/W reset. 1 Interrupt interface INT Output Interrupt Interrupts are requested to the CPU. Polarity of this pin can be selected by register setting. 1 DMA interface SD7/PA7-SD0/ PA0 Input/Output Split Bus / General-purpose Port These pins are used to select either split bus (DMA Interface) or general-purpose port (GPIO). 8 DREQ Output DMA Request This pin is used to request DMA transfer of the D0_FIFO port. Polarity of this pin can be selected by register setting. 1 DACK Input DMA Acknowledge DMA transfer of the D0_FIFO port is enabled in either low or high level. Polarity of this pin can be selected by register setting. 1 DSTB_N Input Split Bus Strobe This pin is used as data strobe signal when the D0_FIFO port has been set to the split bus (DMA Interface). When the RWstb bit of the Data Pin & FIFO/DMA Control Pin Configuration Register 2 is set to “1” (RD/WR strobe mode), this pin is used as data strobe signal. 1 DEND Input/Output Transfer Terminal When the PIPE direction is “IN”, this pin receives transfer complete signal as an input signal from any other peripheral chip or the CPU. When the PIPE direction is “OUT”, this pin indicates the last data transferred as the output signal. Polarity of this pin can be set by a register. 1 USB interface DHP Input/Output USB Hi-Speed Data Connect the D+ signal of USB bus. 1 DHM Input/Output USB Hi-Speed Data Connect the D- signal of USB bus. 1 DFP Input/Output USB Full-Speed Data Connect this pin to DHP via a 43 Ω 1% resistance. 1 DFM Input/Output USB Full-Speed Data Connect this pin to DHM via a 43 Ω 1% resistance. 1 |
Similar Part No. - M66591GP_15 |
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Similar Description - M66591GP_15 |
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