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AN3261 Datasheet(PDF) 10 Page - STMicroelectronics |
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AN3261 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 17 page Typical application diagrams AN3261 10/17 Doc ID 17837 Rev 1 2.6 Reliability note Devices with timings adjusted by external components vs. environmental considerations For device options with timings (tSRC, tREC) adjusted by an external capacitor, there are several additional factors to be considered that may affect the accuracy of the timings. The given specifications apply to the STM65xx device alone, i.e. with an ideal timing capacitor. External tolerances, temperature dependencies and leakages are excluded. The Smart Reset™ devices are designed to meet strict requirements for the lowest possible current consumption and to maintain the common timing constant 10 s/µF, therefore the constant current used to charge the external timing capacitor is very low, in the magnitude of 100 nA. Any external leakage (e.g. poor quality timing capacitors or excessive humidity, especially if dew-point is exceeded and moisture condensation occurs on the PCB tracks) may cause a significant leakage current which is deducted from the constant charging current that the device provides, reducing the effective external timing capacitor charging current which results in extending the tSRC (tREC) timings. To minimize this effect, the PCB tracks between the SRC (TRECADJ) pin and its respective timing capacitor should be as short as possible, properly covered with solder mask and isolated from other tracks (especially VSS) by as great a distance as possible. Also, low-leakage timing capacitors (ceramic or film capacitor) should be used. |
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