In-System Programmable High Density PLD

1048ea_03

1

Functional Block Diagram

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

— 8,000 PLD Gates

— 96 I/O Pins, Eight Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally Compatible with ispLSI 1048C and 1048E

• NEW FEATURES

— 100% IEEE 1149.1 Boundary Scan Testable

— ispJTAG™ In-System Programmable Via IEEE 1149.1

(JTAG) Test Access Port

— User Selectable 3.3V or 5V I/O supports Mixed

— Open Drain Output Option

—

—

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Output Routing Pool

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

A0

A1

A2

A3

A4

A5

A6

A7

Output Routing Pool

Output Routing Pool

CLK

E7 E6 E5 E4 E3 E2 E1 E0

C0 C1 C2 C3 C4 C5 C6 C7

D7

D6

D5

D4

D3

D2

D1

D0

Logic

Array

DQ

DQ

DQ

DQ

Global Routing Pool (GRP)

GLB

0139A/1048EA

Description

The ispLSI 1048EA is a High Density Programmable

Logic Device containing 288 Registers, 96 Universal I/O

pins, eight Dedicated Input pins, four Dedicated Clock

Input pins, two dedicated Global OE input pins, and a

Global Routing Pool (GRP). The GRP provides complete

interconnectivity between all of these elements. The

ispLSI 1048EA features 5V in-system programmability

and in-system diagnostic capabilities via IEEE 1149.1

Test Access Port. The ispLSI 1048EA offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect to provide truly reconfigurable systems. A functional

superset of the ispLSI 1048 architecture, the ispLSI

1048EA device adds user selectable 3.3V or 5V I/O and

open-drain output options.

The basic unit of logic on the ispLSI 1048EA device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 1048EA device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinato-

rial or registered. Inputs to the GLB come from the GRP

and dedicated inputs. All of the GLB outputs are brought

back into the GRP so that they can be connected to the

inputs of any other GLB on the device.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

June 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com