 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
1032E-80LJ Datasheet(PDF) 2 Page - Lattice Semiconductor |
|
||||||||||||||||||||||||||||||
1032E-80LJ Datasheet(HTML) 2 Page - Lattice Semiconductor |
|
|
2 / 16 page  2 Specifications ispLSI and pLSI 1032E Functional Block Diagram Figure 1. ispLSI and pLSI 1032E Functional Block Diagram The devices also have 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to mini- mize overall output switching noise. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI and pLSI 1032E device contains four Megablocks. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI and pLSI 1032E devices are se- lected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distri- bution Network can also be driven from a special clock GLB (C0 on the ispLSI and pLSI 1032E devices). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. RESET Global Routing Pool (GRP) CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 Clock Distribution Network C7 C6 C5 C4 C3 C2 C1 C0 A0 A1 A2 A3 A4 A5 A6 A7 Generic Logic Blocks (GLBs) Megablock Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus *ispEN/NC *ISP Control Functions for ispLSI 1032E Only D7 D6 D5 D4 D3 D2 D1 D0 I/O 35 I/O 34 I/O 33 I/O 32 I/O 0 I/O 1 I/O 2 I/O 3 I/O 12 I/O 13 I/O 14 I/O 15 *SDI/IN 0 *MODE/IN 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 4 I/O 5 I/O 6 I/O 7 I/O 47 I/O 46 I/O 45 I/O 44 GOE 1/IN 5 GOE 0/IN 4 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 B0 B1 B2 B3 B4 B5 B6 B7 |
Similar Part No. - 1032E-80LJ |
|
Similar Description - 1032E-80LJ |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
