Peripheral interconnect matrix

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DocID027699 Rev 2

2.1

Timers block

2.1.1

From TIM to TIM

Some timers are linked together internally for timer synchronization or chaining. When one

timer is configured in Master mode, it can reset, start, stop or clock the counter of an

another timer configured in Slave mode.

A description of this feature is provided in the timer synchronization section and TIM2 option

register (TIM2_OR) of RM0385 reference manual.

The output (from Master) is on TIM_TRGO signal following a configurable timer event. The

input (to Slave) is on TIM_ITR0/ITR1/ITR2/ITR3 signal events.

Figure 2 gives an overview of the trigger selection and the Master mode selection blocks.

Figure 2. Master/slave timer overview

For more details on the possible master/slave connections, refer to TIMx internal trigger

connection tables of RM0385 reference manual.

----

----

----

--

X

-

---

----

----

----

--

X

-

---

EXTI

----

----

----

--

X

X

X

X

X

Table 1. STM32F7 Series peripheral interconnect matrix (continued)

Users

Timers

DMA

Analog

Generators

ADC

DAC

1

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