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UPD75036CW Datasheet(PDF) 10 Page - NEC |
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UPD75036CW Datasheet(HTML) 10 Page - NEC |
10 / 58 page 10 µPD75036 3.2 NON-PORT PINS (2/2) Pin X1, X2 XT1, XT2 RESET IC VDD VSS I/O circuit typeNote – – – – – Shared pin – – – – – – When reset – – – – – – Input/ output Function Crystal/ceramic connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. Crystal connection for subsystem clock genera- tion. When external clock signal is used, it is applied to XT1, and its reverse phase signal is applied to XT2, XT1 can be used as a 1-bit input (test). System reset input Internally connected. (To be directly connected to VDD) Positive power supply GND potential Input Input Input – – – Note The circle ( ) indicates the Schmitt trigger input. B |
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