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LT1680 Datasheet(PDF) 10 Page - Linear Technology |
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LT1680 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 16 page  10 LT1680 capacitor CSS, the start up delay time to full available average current will be: tSS = (1.5)(105)(CSS) Shutdown Function—Input Undervoltage Detect and Threshold Hysteresis The LT1680 RUN/SHDN pin uses a bandgap generated reference threshold of about 1.25V. This precision thresh- old allows use of the RUN/SHDN pin for both logic-level shutdown applications and analog monitoring applica- tions such as power supply sequencing. Because an LT1680 controlled converter is a power trans- fer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourc- ing capabilities of that supply, causing the system to lock- up in an undervoltage state. Input supply start-up protection can be achieved by enabling the RUN/SHDN pin using a resistor divider from the input supply to ground. Setting the divider output to 1.25V when the supply is almost fully enabled prevents the LT1680 regulator from drawing large currents until the input supply is able to supply the required power. If additional hysteresis is desired for the enable function, an external feedback resistor can be used from the LT1680 regulator output. If connection to the regulator output is not desired, the 5VREF internal supply pin can be used. Figure 3 shows an input supply sequencing configuration on a 24V input converter. This configuration yields an enable condition of 90% VIN (~ 21.5V) with about 10% threshold hysteresis. The shutdown function can be disabled by connecting the RUN/SHDN pin to the 12VIN rail. This pin is internally Figure 3. Input Supply Sequencing Programming TIMING RESISTOR (k Ω) 3 7 11 15 19 23 27 31 35 39 43 47 200 180 160 140 120 100 80 60 40 1680 F02 CCT = 0.68nF CCT = 1nF CCT = 2.2nF CCT = 1.5nF Figure 2. Operating Frequency vs RCT, CCT Average Current Limit The average current limit function is implemented using an external capacitor (CAVG) connected either from the IAVG pin to the VC pin or from the IAVG pin to SGND. This capacitor forms a single-pole integrator with the 50k Ω output impedance of the IAVG pin. Precise integration frequencies can be determined using a ground reference integration capacitor using the relation: f–3dB = (3.2)(10–6)/CAVG Connecting a capacitor from the IAVG pin to the VC pin uses an internal gain block to form an active integrator circuit, minimizing the required capacitance for stable operation. A typical value for this integration capacitor is 220pF from IAVG to VC. Shorting the IAVG pin to SGND will disable the average current limit function. Soft Start Programming The current control pin (VC) limits sensed inductor current to zero at voltages less than a transistor VBE, to full average current limit at VC = VBE + 1.8V. This generates a 1.8V full regulation range for average load current. An internal voltage clamp forces the VC pin to a VBE – 100mV above the SS pin voltage. This 100mV “dead zone” assures 0% duty cycle operation at the start of the soft start cycle or when the soft start pin is pulled to ground. Given the typical soft start current of 8 µA and a soft start timing VIN 24V 16 11 160k 390k 10k 1680 F03 5VREF RUN/SHDN LT1680 APPLICATIO S I FOR ATIO |
Similar Part No. - LT1680_15 |
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Similar Description - LT1680_15 |
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