11

LT1107

Figure 7 details current limit circuitry. Sense transistor A1,

whose base and emitter are paralleled with power switch

Q2, is ratioed such that approximately 0.5% of Q2’s

collector current flows in Q1’s collector. This current is

passed through internal 80

Ω resistor R1 and out through

turning off the switch. Delay through this circuitry is

approximately 800ns. The current trip point becomes less

accurate for switch ON times less than 3

µs. Resistor

values programming switch ON time for 800ns or less will

cause spurious response in the switch circuitry although

the device will still maintain output regulation.

Using the Gain Block

The gain block (GB) on the LT1107 can be used as an error

amplifier, low-battery detector or linear post regulator.

The gain block itself is a very simple PNP input op amp with

an open collector NPN output. The negative input of the

gain block is tied internally to the 1.25V reference. The

positive input comes out on the SET pin.

Arrangement of the gain block as a low-battery detector is

straightforward. Figure 8 shows hookup. R1 and R2 need

only be low enough in value so that the bias current of the

SET input does not cause large errors. 33k for R2 is

adequate. R3 can be added to introduce a small amount of

hysteresis. This will cause the gain block to “snap” when

the trip point is reached. Values in the 1M to 10M range are

optimal. The addition of R3 will change the trip point,

however.

be reduced significantly by placing the gain block in front

of the FB input as shown in Figure 9. This effectively

reduces the comparator hysteresis by the gain of the gain

block. Output ripple can be reduced to just a few millivolts

using this technique. Ripple reduction works with step-

down or inverting modes as well. For this technique to be

effective, output capacitor C1 must be large, so that each

1000

µF is a good starting value. C1 should be a low ESR

type as well.

S

APPLICATI

I FOR ATIO

1107 F07

SW2

SW1

DRIVER

OSCILLATOR

R1

80

Ω

(INTERNAL)

(EXTERNAL)

Q3

Q2

Q1

Figure 7. LT1107 Current Limit Circuitry

L1

1107 F09

D1

R3

270k

+

R2

R1

C1

LT1107

GND

SW2

SET

SW1

FB

AO

+ 1 1.25V

R2

R1

()( )

Figure 9. Output Ripple Reduction Using Gain Block

Figure 8. Setting Low-Battery Detector Trip Point

1107 F08

R1

R2

1.25V

REF

SET

GND

LT1107

47k

5V

TO

PROCESSOR

AO

R3

R1 =

R2 = 33k

R3 = 1.6M

()

35.1

µA

+

–

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.