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LT1122DCJ8 Datasheet(PDF) 7 Page - Linear Technology

Part # LT1122DCJ8
Description  Fast Settling, JFET Input Operational Amplifier
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT1122DCJ8 Datasheet(HTML) 7 Page - Linear Technology

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7
LT1122
S
APPLICATI
I FOR ATIO
When the feedback around the op amp is resistive (RF), a
pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN ≈ 4pF). In low closed loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capacitor
(CF) in parallel with RF eliminates this problem. With
RS (CS + CIN) = RFCF, the effect of the feedback pole is
completely removed.
Settling Time Measurements
Settling time test circuits shown on some competitive
devices’ data sheets require:
1. A “flat top” pulse generator. Unfortunately, flat top
pulse generators are not commercially available.
2. A variable feedback capacitor around the device under
test. This capacitor varies over a four to one range.
Presumably, as each op amp is measured for settling
time, the capacitor is fine tuned to optimize settling
time for that particular device.
3. A small inductor load to optimize settling.
The LT1122’s settling time is 100% tested in the test
circuit shown. No “flat top” pulse generator is required.
The test circuit can be readily constructed, using commer-
cially available ICs. Of course, standard high frequency
board construction techniques should be followed. All
LT1122s are measured with a constant feedback capaci-
tor. No fine tuning is required.
Speed Boost/Overcompensation Terminal
Pin 8 of the LT1122 can be used to change the input stage
operating current of the device. Shorting pin 8 to the
positive supply (Pin 7) increases slew rate and bandwidth
by about 25%, but at the expense of a reduction in phase
margin by approximately 18 degrees. Unity gain capaci-
tive load handling decreases from typically 500pF to
100pF.
Conversely, connecting a 15k resistor from pin 8 to
ground pulls 1mA out of pin 8 (with V+ = 15V). This
reduces slew rate and bandwidth by 25%. Phase margin
and capacitive load handling improve; the latter typically
increasing to 800pF.
High Speed Operation
As with most high speed amplifiers, care should be taken
with supply decoupling, lead dress and component
placement.
The power supply connections to the LT1122 must main-
tain a low impedance to ground over a bandwidth of
20MHz. This is especially important when driving a signifi-
cant resistive or capacitive load, since all current delivered
to the load comes from the power supplies. Multiple high
quality bypass capacitors are recommended for each
power supply line in any critical application. A 0.1
µF
ceramic and a 1
µF electrolytic capacitor, as shown, placed
as close as possible to the amplifier (with short lead
lengths to power supply common) will assure adequate
high frequency bypassing, in most applications.
RS
CS
CIN
RF
CF
OUTPUT
+
LT1122•TA04
µ
V+
7
2
6
3
4
1 F
µ
0.1 F
µ
1 F
µ
0.1 F
+
V–
LT1122
LT1122•TA03
+
+
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.


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