UPD75066GB datasheet(9/68 Pages) NEC

Part #	UPD75066GB

Description	4-BIT SINGLE-CHIP MICROCOMPUTER

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Manufacturer	NEC [NEC]

Direct Link	http://www.nec.com/

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9

µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

Pin name

TI0

PTO0

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0 - KR3

AN0 - AN3

AN4 - AN7

AVREF

AVSS

X1, X2

XT1, XT2

RESET

IC

VDD

VSS

I/O circuit

typeNote 1

-C

E-B

-A

-B

-C

-D

Y-A

-D

Z

–

Shared

with

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60 - P63/

AN4 - AN7

P110 - P113

P60 - P63/

KR0 - KR3

–

When reset

–

Input

–

Input

–

Input/

output

Input

I/O

Input

I/O

Input

I/O

Input

–

Input

–

Function

Input for receiving external event pulse signal for

timer/event counter

Timer/event counter output

Clock output

Output frequency selectable

(for buzzer output or system clock trimming)

Serial clock I/O

Serial data output

Serial bus I/O

Serial data input

Serial bus I/O

Edge-detective vectored interrupt input

(both rising and falling edges enabled)

Edge-detective vectored interrupt input

(detection edge selectable)

Edge-detective testable input

(rising edge detection)

Parallel falling edge detection testable input

For A /D converter only

Crystal/ceramic connection for main system clock

generation. When external clock signal is used,

the signal should be applied to X1, and its reverse

phase signal to X2.

Crystal connection for subsystem clock genera-

tion.

When external clock signal is used, the

signal should be applied to XT1, and its reverse

phase signal to XT2. XT1 can be used as a 1-bit

input (test).

System reset input

Internally connected.

(Connect this pin directly to VDD)

Positive power supply

GND potential

3.2

Non-Port Pins

8-bit analog input

Reference voltage input

GND potential

B

F

M

B

Y

B

Note 2

Note 3

Notes 1. The circle (

) indicates the Schmitt trigger input.

2. Clock synchronous

3. Asynchronous

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UPD75066GB Datasheet(PDF) 9 Page - NEC

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