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LT4256-2 Datasheet(PDF) 6 Page - Linear Technology |
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LT4256-2 Datasheet(HTML) 6 Page - Linear Technology |
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6 / 16 page  LT4256-1/LT4256-2 6 425612fa PI FU CTIO S UV (Pin 1): Undervoltage Sense. UV is an input that enables the output voltage. When UV is driven above 4V, GATE will start charging and the output turns on. When UV goes below 3.6V, GATE discharges and the output shuts off. Pulsing UV low for a minimum of 5 µs after a current limit fault cycle resets the fault latch (LT4256-1) and allows the part to turn back on. This command is only accepted after TIMER has discharged below 0.65V. To disable UV sens- ing, connect UV to a voltage beween 5V and 44V. FB (Pin 2): Power Good Comparator Input. FB monitors the output voltage through an external resistive divider. When the voltage on FB is lower than the high-to-low threshold of 3.99V, PWRGD is pulled low and released when FB is pulled above the 4.45V low-to-high threshold. The voltage present on FB affects foldback current limit (see Figure 7 and related discussion). PWRGD (Pin 3): Power Good Output. PWRGD is pulled low whenever the voltage on FB falls below the 3.99V high- to-low threshold voltage. It goes into a high impedance state when the voltage on FB exceeds the low-to-high threshold voltage. An external pull-up resistor can pull PWRGD to a voltage higher or lower than VCC. GND (Pin 4): Device Ground. This pin must be tied to a ground plane for best performance. TIMER (Pin 5): Timing Input. An external timing capacitor from TIMER to GND programs the maximum time the part is allowed to remain in current limit. When the part goes into current limit, a 105 µA pull-up current source starts to charge the timing capacitor. When the voltage on TIMER reaches 4.65V (typ), GATE pulls low; the TIMER pull-up current will be turned off and the capacitor is discharged by a 3 µApull-downcurrent.WhenTIMERfallsbelow0.65V (typ), GATE turns on again for the LT4256-2. UV must be cycled low after TIMER has discharged below 0.65V (typ) to reset the LT4256-1. If UV is not cycled low (LT4256-1), GATE remains latched off and TIMER is discharged to near GND. Under an output short-circuit condition, the LT4256-2 cycles on and off with a 3% duty cycle. GATE (Pin 6): High Side Gate Drive for the External N- Channel MOSFET. An internal charge pump guarantees at least 10V of gate drive for VCC supply voltages above 20V and 4.5V of gate drive for VCC supply voltages between 10.8V and 20V. The rising slope of the voltage on GATE is set by an external capacitor connected from GATE to GND and an internal 32 µA pull-up current source from the charge pump output. If the current limit is reached, the GATE voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. If the TIMER voltage ever exceeds 4.65V, GATE is pulled low. GATE is also pulled to GND whenever UV is pulled low, the VCC supplyvoltagedropsbelowtheexternallyprogrammed undervoltage threshold, or VCC drops below the internal UVLO threshold (9.8V). GATE is clamped internally to a maximum voltage of 11.6V (typ) above VCC under normal operating conditions. Driv- ing this pin beyond the clamp voltage may damage the part. A Zener diode is needed between the gate and source of the external MOSFET to protect its gate oxide under instantaneous short-circuit conditions. See Applications Information. SENSE (Pin 7): Current Limit Sense Input. A sense resistor is placed in the supply path between VCC and SENSE. The current limit circuit regulates the voltage across the sense resistor (VCC – SENSE) to 55mV while in current limit when FB is 2V or higher. If FB drops below 2V, the regulated voltage across the sense resistor de- creases linearly to 14mV when FB is 0V. To defeat current limit, connect SENSE to VCC. VCC (Pin 8): Input Supply Voltage. The positive supply input ranges from 10.8V to 80V for normal operation. ICC is typically 1.8mA. An internal circuit disables the LT4256-1/LT4256-2 for inputs less than 9.8V (typ). |
Similar Part No. - LT4256-2_15 |
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Similar Description - LT4256-2_15 |
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