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UPD75308B Datasheet(PDF) 11 Page - NEC |
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UPD75308B Datasheet(HTML) 11 Page - NEC |
11 / 76 page µPD75304B,75306B,75308B 11 XT1 XT2 RESET NC *5 VDD VSS Function External event pulse input pin to timer/event counter Timer/event counter output pin Clock output pin Fixed frequency output pin (for buzzer or system clock trimming) Serial clock input/output pin Serial data output pin Serial bus input/output pin Serial data input pin Serial bus input/output pin Edge detection vectored interrupt input pin (both rising edge and falling edge detection effective) Edge detection vectored interrupt input pin (detection edge selectable) Edge detection testable input pin (rising edge detection) Parallel falling edge detection testable input pin Parallel falling edge detection testable input pin Segment signal output pin Segment signal output pin Common signal output pin LCD drive power supply pin On-chip split resistor (mask option) External split resistor cut output pin External expansion driver drive clock output pin External expansion driver synchronization clock output pin Main system clock oscillation crystal/ceramic connection pin. For external clock, the external clock signal is input to X1 and its opposite phase is input to X2. Subsystem clock oscillation crystal connection pin. For external clock, the external clock signal is input to XT1 and XT2 is opened. XT1 can be used as a 1-bit input (test) pin. System reset input pin NO CONNECTION Positive power supply pin GND potential pin Pin Name TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 INT1 INT2 KR0 to KR3 KR4 to KR7 S0 to S23 S24 to S31 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL *4 3.2 NON-PORT PINS Dual- Function Pin P13 P20 P22 P23 P01 P02 P03 P00 P10 P11 P12 P60 to P63 P70 to P73 — BP0 to BP7 — — — P30 P31 — — — — — — — Clock synchronous system Asynchronous Asynchronous *1. : Schmitt trigger input 2. Display outputs are selected with VLCX shown below as the input source. S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, the level of each display output depends on the display output and VLCX external circuit. Input/Output Input Input/output Input/output Input/output Input/output Input/output Input/output Input Input Input Input/output Input/output Output Output Output — Output Input/output Input/output Input Input — Input — — — Input Input Input Input Input Input Input Input Input Input Input Input *2 *2 *2 — *3 Input Input — — — — — — SYNC *4 X1, X2 After Reset I/O Circuit Type *1 B - C E - B E - B E - B F - A F - B M - C B B - C B - C F - A F - A G - A G - C G - B — — E - B E - B — — B — — — |
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