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LTC1063MJ8 Datasheet(PDF) 7 Page - Linear Technology |
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LTC1063MJ8 Datasheet(HTML) 7 Page - Linear Technology |
7 / 12 page 7 LTC1063 PI FU CTIO S filter’s DC output offset (Figure 1). RIN should, however, be limited to a maximum value (Table 1), otherwise the filter’s passband flatness will be affected. Refer to the Applica- tions Information section for more details. Output Pin (Pin 7, N Package) Pin 7 is the filter output. This pin can typically source over 20mA and sink 2mA. Pin 7 should not drive long coax cables, otherwise the filter’s total harmonic distortion will degrade. Clock Input Pin (Pin 5, N Package) An external clock when applied to pin 5 tunes the filter cutoff frequency. The clock-to-cutoff frequency ratio is 100:1. The high (VHIGH) and low (VLOW) clock logic threshold levels are illustrated in Table 2. Square wave clocks with duty cycles between 30% and 50% are strongly recommended. Sinewave clocks are not recommended. Clock Output Pin (Pin 4, N Package) Any external clock applied to the clock input pin appears at the clock output pin. The duty cycle of the clock output equals the duty cycle of the external clock applied to the clock input pin. The clock output pin swings to the power supply rails. When the LTC1063 is used in a self-clocking mode, the clock of the internal oscillator appears at the clock output pin with a 30% duty cycle. The clock output pin can be used to drive other LTC1063s or other ICs. The maximum capacitance, CL(MAX), the clock output pin can drive is illustrated in Figure 3. Table 1. RIN(MAX) vs Clock and Power Supply RIN(MAX) VS = ±7.5V VS = ±5V VS = ±2.5V fCLK = 4MHz 2.2k – – fCLK = 3MHz 3.4k 2.9k – fCLK = 2MHz 5.5k 5k 2.7k fCLK = 1MHz 11k 11k 9.2k fCLK = 500kHz 24k 23k 21k fCLK = 100kHz 120k 120k 110k Figure 1. VIN VOUT 1063 F01 V– V+ RIN 1 2 3 4 8 7 6 5 LTC1063 fCLK Table 2. Clock Pin Threshold Levels POWER SUPPLY VHIGH VLOW VS = ±2.5V 1.5V 0.5V VS = ±5V 3V 1V VS = ±7.5V 4.5V 1.5V VS = ±8V 4.8V 1.6V VS = 5V, 0V 4V 3V VS = 12, 0V 9.6V 7.2V VS =15V, 0V 12V 9V Figure 2. Test Circuit for THD CLOCK FREQUENCY (MHz) 1 200 180 160 140 120 100 80 60 40 20 0 310 1063 F03 24 5 6 78 9 VS = ±2.5V VS = ±5V VS = ±7.5V TA = 25°C Figure 3. Maximum Load Capacitance at the Clock Output Pin V– 50k V+ 0.1 µF VOUT 1063 TC01 0.1 µF CLOCK IN – + LT1022 20pF VIN 50k 8 7 6 5 1 2 3 4 LTC1063 TEST CIRCUIT |
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