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LTC1067 Datasheet(PDF) 8 Page - Linear Technology |
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LTC1067 Datasheet(HTML) 8 Page - Linear Technology |
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8 / 20 page  8 LTC1067/LTC1067-50 PIN FUNCTIONS SA, SB (Pins 4, 13): Summing Inputs. The summing pins’ connection, along with the other resistor connections, determine the circuit topology (mode) of each 2nd order section. These pins should never be left floating. LPA, BPA, HPA/NA, HPB/NB, BPB, LPB (Pins 5, 6, 7, 10, 11, 12): Output Pins. Each 2nd order section of the LTC1067 has three outputs which typically source 33mA and sink 2mA. Driving coaxial cable, capacitive loads or resistive loads less than 10k will degrade the total har- monic distortion performance of any filter design. Refer to Output Loading in the Applications Information section for more details. When evaluating the distortion or noise performance of a filter, the output should be buffered with a wideband amplifier. INV A, INV B (Pins 8, 9): Inverting Input. These pins are the high impedance inverting inputs of internal op amps. They are susceptible to stray capacitance coupling to low impedance nodes such as signal outputs and power supply lines. Resistors that are connected from a signal output to the inverting input pin should be located as close to the inverting input as possible. AGND (Pin 15): Analog Ground. The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation Pin 15 is connected to the analog ground plane. For single supply operation Pin 15 should be bypassed to the analog ground plane with at least a 1 µF capacitor. An on-chip resistive voltage divider sets the bias at one-half of the supply. CLK (Pin 16): Clock Input. Any CMOS logic clock source with a square-wave output and a 50% duty cycle ( ±10%) is an adequate clock source for the device. The power supply for the clock source should not be the filter’s power supply. The analog ground for the filter should be con- nected to the clock’s ground at a single point only. Table 1 shows the clock’s low and high level threshold values for dual supply or single supply operation. Logic low level signals must be greater than the negative supply voltage. With a ±5V power supply, the clock levels may be either ±5V or 0V to 5V. Logic high level signals should be less than the positive supply voltage. However, when the positive supply voltage is either 3V or 3.3V, the clock signal can be as high as 5.5V. Table 1. Clock Source High and Low Threshold Levels POWER SUPPLY HIGH LEVEL LOW LEVEL ±5V ≥ 2.2V ≤ 0.50V Single 5V ≥ 2.2V ≤ 0.50V Single 3V, 3.3V ≥ 2V ≤ 0.40V Sine waves are not recommended for the clock input. The clock signal should be routed from the right side of the IC package to avoid coupling to any power supply lines or input or output signal paths. A 200 Ω resistor between the clock source and Pin 16 will slow down the rise and fall times of the clock to reduce charge coupling of the clock. This will result in less clock feedthrough noise on the output signal. BLOCK DIAGRA + – – + INV A INV B CLK V – V+ V+ 1 3 8 14 HPA/NA BPA LPA ∑ SA HPB/NB BPB LPB ∑ SB AGND 15k 15k 1067 BD + + – – 15 9 16 10 13 11 12 7 4 65 |
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Similar Description - LTC1067 |
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